Patents Assigned to Soitec
  • Patent number: 8951887
    Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Soitec
    Inventors: Fabrice Letertre, Didier Landru
  • Patent number: 8946053
    Abstract: A method for reducing irregularities at a surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 ?m and 600 ?m.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: February 3, 2015
    Assignee: Soitec
    Inventors: Daniel Delprat, Carine Duret, Nadia Ben-Mohamed, Fabrice Lallement
  • Publication number: 20150027519
    Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate, providing a second substrate having a lower surface and an upper surface, forming at least one first solar cell layer on the first substrate to obtain a first wafer structure, forming at least one second solar cell layer on the upper surface of the second substrate to obtain a second wafer structure, and bonding the first wafer structure to the second wafer structure, wherein the at least one first solar cell layer is bonded to the lower surface of the second substrate and removing the first substrate.
    Type: Application
    Filed: March 13, 2013
    Publication date: January 29, 2015
    Applicant: SOITEC
    Inventors: Bruno Ghyselen, Chantal Arena, Frank Dimroth, Andreas W. Bett
  • Publication number: 20150014824
    Abstract: The present invention relates to a method for fabricating a substrate for a semiconductor device comprising an interface region between a first layer and a second layer having different electrical properties and an exposed surface, wherein at least the second layer includes defects and/or dislocations, the method comprising the steps of: a) removing material at one or more locations of the defects and/or dislocations, thereby forming pits, wherein the pits intersect the interface region, and b) passivating the pits. The invention also relates to a corresponding semiconductor device structure.
    Type: Application
    Filed: December 15, 2011
    Publication date: January 15, 2015
    Applicant: SOITEC
    Inventor: Oleg Kononchuk
  • Publication number: 20150014822
    Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.
    Type: Application
    Filed: February 18, 2013
    Publication date: January 15, 2015
    Applicant: SOITEC
    Inventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert
  • Patent number: 8932938
    Abstract: A method of producing a composite structure comprises a step of producing a first layer of microcomponents on one face of a first substrate, the first substrate being held flush against a holding surface of a first support during production of the microcomponents, and a step of bonding the face of the first substrate comprising the layer of microcomponents onto a second substrate. During the bonding step, the first substrate is held flush against a second support, the holding surface of which has a flatness that is less than or equal to that of the first support used during production of the first layer of microcomponents.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: January 13, 2015
    Assignee: Soitec
    Inventors: Arnaud Castex, Marcel Broekaart
  • Patent number: 8927320
    Abstract: A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to a peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: January 6, 2015
    Assignee: Soitec
    Inventors: Chrystelle Lagahe Blanchard, Marcel Broekaart, Arnaud Castex
  • Publication number: 20150001568
    Abstract: A device for back-scattering an incident light ray, including: a host substrate; a structured layer; a first face in contact with a front face of the host substrate; a second flat face parallel to the first face; a first material and a second material which form, in a mixed plane, alternating surfaces at least one of whose dimensions is between 300 nm and 800 nm, the mixed plane is between the first and second face of the structured layer; wherein the refractive index of the first and of the second material are different, the structured layer is covered by a specific layer, the specific layer is made of a material which is different from the first and second materials of the structured layer, and the specific layer is crystalline and semi-conductive.
    Type: Application
    Filed: January 4, 2013
    Publication date: January 1, 2015
    Applicants: Commissariaat a I'energie atomique et aux ene alt, SOITEC
    Inventors: Yohan Desieres, Philippe Gilet, Pascal Guenard
  • Patent number: 8921239
    Abstract: A process for recycling a support substrate of a material substantially transparent to at least a wavelength of electromagnetic radiation. The process includes providing an initial substrate; forming an intermediate layer on a bonding face of the support substrate having an initial roughness, with the intermediate layer being of a material substantially transparent to at least a wavelength of electromagnetic radiation; forming an electromagnetic radiation absorbing layer either on the bonding face of the initial substrate or on the intermediate layer; bonding the initial substrate to the support substrate via the electromagnetic radiation absorbing layer; and irradiating the electromagnetic radiation absorbing layer through the support substrate and the intermediate layer to induce separation of the support substrate from the initial substrate.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: December 30, 2014
    Assignee: Soitec
    Inventor: Anne Laure Belle
  • Patent number: 8916483
    Abstract: Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material, such as GaN, over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 23, 2014
    Assignee: SOITEC
    Inventor: Christiaan J. Werkhoven
  • Publication number: 20140370695
    Abstract: The present invention relates to a method for fabricating a semiconductor structure comprising a semiconductor layer and a metallic layer, to improve the breakdown voltage properties of the device and reduce leakage currents, the method comprises the steps of a) providing a semiconductor layer comprising defects and/or dislocations; b) removing material at one or more locations of the defects and/or dislocations thereby forming pits in the semiconductor layer, c) passivating the pits, and c) providing the metallic layer over the semiconductor layer. The invention also relates to a corresponding semiconductor structure.
    Type: Application
    Filed: December 15, 2011
    Publication date: December 18, 2014
    Applicant: SOITEC
    Inventor: Oleg Kononchuk
  • Patent number: 8912081
    Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: December 16, 2014
    Assignee: SOITEC
    Inventor: Bruce Faure
  • Publication number: 20140339681
    Abstract: The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing: a support substrate formed from a material that is at least partially transparent at a determined wavelength; a layer to be separated; and a separation layer interposed between the support substrate and the layer to be separated, the separation layer being adapted to be separated by exfoliation under the action of radiation having a wavelength corresponding to the determined wavelength. Furthermore, the method comprises, during the step for forming the composite step, a treatment step modifying the optical properties in reflection at the interface between the support substrate and the separation layer or on the upper face of the support substrate.
    Type: Application
    Filed: July 18, 2012
    Publication date: November 20, 2014
    Applicant: SOITEC
    Inventors: Christophe Figuet, Christophe Gourdel
  • Patent number: 8887650
    Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 18, 2014
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Patent number: 8890299
    Abstract: Embodiments of the invention include methods and structures for fabricating a semiconductor structure and, particularly, for improving the planarity of a bonded semiconductor structure comprising a processed semiconductor structure and a semiconductor structure.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: November 18, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Radu Ionut
  • Publication number: 20140326416
    Abstract: The disclosure relates to a method for separating a layer from a composite structure, the structure comprising a composite stack formed from at least a support substrate, which is partially transparent at a determined wavelength, the layer to be separated and a separation layer interposed between the support substrate and the layer to be separated, the method comprising irradiation of the separation layer through the support substrate by means of incident light ray at the determined wavelength in order to induce weakening or separation by exfoliation of the separation layer, the light ray being inclined so as to form an angle of incidence ? such that ?>?min, where ?min=sin?1((n1/n0)sin(tan?1(s/2h))), n1 and n0, respectively, being the refractive index of the support substrate and the refractive index of the external medium in contact with the support substrate, from which the ray comes, S being the width of the ray and h being the thickness of the support substrate.
    Type: Application
    Filed: July 18, 2012
    Publication date: November 6, 2014
    Applicant: SOITEC
    Inventor: Didier Landru
  • Publication number: 20140327013
    Abstract: The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of BwAlxGayInzN, growth of a layer of BwAlxGayInzN, (c3) growth of an intermediate layer of BwAlxGayInzN, at least one of the layers formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer of GaN.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 6, 2014
    Applicants: SOITEC, OMMIC, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
    Inventors: David Schenk, Alexis Bavard, Yvon Cordier, Eric Frayssinet, Mark Kennard, Daniel Rondi
  • Publication number: 20140321225
    Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.
    Type: Application
    Filed: November 14, 2012
    Publication date: October 30, 2014
    Applicant: SOITEC
    Inventors: Richard Ferrant, Joerg Vollrath, Roland Thewes, Wolfgang Hoenlein, Hofmann Franz, Gerhard Enders
  • Patent number: 8871611
    Abstract: A method for bonding first and second wafers by molecular adhesion. The method includes placing the wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure above which initiation of bonding wave propagation is prevented, bringing the first wafer and the second wafer into alignment and contact, and spontaneously initiating the propagation of a bonding wave between the wafers after they are in contact solely by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: October 28, 2014
    Assignee: Soitec
    Inventor: Marcel Broekaart
  • Patent number: 8866305
    Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: October 21, 2014
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu