Patents Assigned to Soitec
  • Patent number: 8778777
    Abstract: A method for manufacturing a heterostructure for applications in the fields of electronics, photovoltaics, optics or optoelectronics, by implanting atomic species in a donor substrate so as to form an embrittlement area therein, assembling a receiver substrate on the donor substrate, wherein the receiver substrate has a larger thermal expansion coefficient than that of the donor substrate, detaching a rear portion of the donor substrate along the embrittlement area so as to transfer a thin layer of interest of the donor substrate onto the receiver substrate, and applying a detachment annealing after assembling and but before detaching, in order to facilitate the detaching. The detachment annealing includes the simultaneous application of a first temperature to the donor substrate and a second temperature different from the first to the receiver substrate; with the first and second temperatures being selected to reduce the tensile stress condition of the donor substrate.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: July 15, 2014
    Assignee: Soitec
    Inventor: Mark Kennard
  • Patent number: 8772875
    Abstract: A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: July 8, 2014
    Assignees: Corning Incorporated, SOITEC
    Inventors: Nadia Ben Mohamed, Ta-ko Chuang, Jeffrey Scott Cites, Daniel Delprat, Alexander Usenko
  • Publication number: 20140183601
    Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that is distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into the donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.
    Type: Application
    Filed: June 20, 2012
    Publication date: July 3, 2014
    Applicant: SOITEC
    Inventors: Fabrice Lallement, Christophe Figuet, Daniel Delprat
  • Patent number: 8765508
    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8765571
    Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing a semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Frederic Allibert
  • Patent number: 8759196
    Abstract: A method for preparing a substrate for detaching a layer by irradiation of the substrate with a light flux for heating a buried region of the substrate and bringing about decomposition of the material of that region to detach the detachment layer. The method includes fabricating an intermediate substrate including a first buried layer, and a second covering layer that covers all or part of the first layer, with the covering layer being substantially transparent to the light flux and with the buried layer formed by implantation of particles into the substrate, followed by absorbing the flux, and selectively and adiabatically irradiating a treated region of the buried layer until at least partial decomposition of the material constituting it ensues.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 24, 2014
    Assignee: Soitec
    Inventor: Michel Bruel
  • Patent number: 8759881
    Abstract: A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1, a bonding layer, a first seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, a second seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and an active layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 ?, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm2.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: June 24, 2014
    Assignee: Soitec
    Inventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuck
  • Patent number: 8754505
    Abstract: A method of producing a heterostructure by bonding at least one first substrate having a first thermal expansion coefficient onto a second substrate having a second thermal expansion coefficient, with the first thermal expansion coefficient being different from the second thermal expansion coefficient. Prior to bonding, trenches are formed in one of the two substrates from the bonding surface of the substrate. The trenches are filled with a material having a third thermal expansion coefficient lying between the first and second thermal expansion coefficients.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: June 17, 2014
    Assignee: Soitec
    Inventor: Cyrille Colnat
  • Publication number: 20140158041
    Abstract: The invention concerns a method for fabricating a substrate in semiconductor material characterized in that it comprises the steps of: starting from a donor substrate in a first semiconductor material at an initial temperature, contacting a surface of the donor substrate with a bath of a second semiconductor material held in the liquid state at a temperature higher than the initial temperature, the second semiconductor material being chosen so that its melting point is equal to or lower than the melting point of the first semiconductor material, solidifying the bath material on the surface to thicken the donor substrate with a solidified layer. The invention also concerns a device for implementing the method.
    Type: Application
    Filed: July 25, 2012
    Publication date: June 12, 2014
    Applicant: SOITEC
    Inventor: Michel Bruel
  • Patent number: 8741385
    Abstract: The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: June 3, 2014
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, Jr., Ed Lindow
  • Patent number: 8742428
    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: June 3, 2014
    Assignee: Soitec
    Inventors: Christophe Figuet, Pierre Tomasini
  • Publication number: 20140144486
    Abstract: A wasted heat harvesting device for harvesting electricity including a switching device configured to convey a magnetic field from a first region to at least a second region when the temperature of the switching device crosses a predetermined temperature.
    Type: Application
    Filed: July 20, 2012
    Publication date: May 29, 2014
    Applicant: SOITEC
    Inventors: Rainer Krause, Bruno Ghyselen
  • Patent number: 8735946
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 27, 2014
    Assignee: Soitec
    Inventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Publication number: 20140138796
    Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: Soitec
    Inventor: Christiaan J. Werkhoven
  • Patent number: 8728913
    Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions that are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 20, 2014
    Assignee: Soitec
    Inventors: Sébastien Kerdiles, Walter Schwarzenbach, Aziz Alami-Idrissi
  • Patent number: 8728863
    Abstract: Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thinner layer of material on a thicker substrate body, and forming a plurality of through wafer interconnects through the layer of material. A first semiconductor structure may be bonded over the thin layer of material, and at least one conductive feature of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect, an optical interconnect, and a fluidic interconnect may be formed in the transferred layer of material. A second semiconductor structure may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: May 20, 2014
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Mariam Sadaka
  • Patent number: 8722515
    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: May 13, 2014
    Assignee: Soitec
    Inventors: Chrystelle Lagahe, Bernard Aspar
  • Patent number: 8716105
    Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: May 6, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru
  • Patent number: 8697493
    Abstract: Methods of directly bonding a first semiconductor structure to a second semiconductor structure include directly bonding at least one device structure of a first semiconductor structure to at least one device structure of a second semiconductor structure in a conductive material-to-conductive material direct bonding process. In some embodiments, at least one device structure of the first semiconductor structure may be caused to project a distance beyond an adjacent dielectric material on the first semiconductor structure prior to the bonding process. In some embodiments, one or more of the device structures may include a plurality of integral protrusions that extend from a base structure. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: April 15, 2014
    Assignee: Soitec
    Inventor: Mariam Sadaka
  • Patent number: 8692260
    Abstract: A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer formed on a support substrate, and a seed layer formed on the intermediate layer. An active device layer is grown or attached to the seed layer, or to a light confinement layer on the seed layer. The intermediate layer may be formed directly on the support layer, or may be formed by thinning an attached wafer of the intermediate material, which is then thinned to a desired thickness.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: April 8, 2014
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan J. Werkhoven