Patents Assigned to STMicroelectronic S.A.
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Patent number: 8754753Abstract: The selection of at least one back-modulation element of an electromagnetic transponder from among a plurality of resistive and/or capacitive modulation elements of the load of an oscillating circuit of the transponder, including selecting the modulation element(s) according to a binary message received from a read/write terminal.Type: GrantFiled: November 3, 2010Date of Patent: June 17, 2014Assignee: STMicroelectronics S.A.Inventor: Jean-Pierre Enguent
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Patent number: 8755741Abstract: A satellite receive unit for receiving a plurality of satellite signals from a plurality of satellites, the satellite receive unit including: a plurality of low noise blocks each for receiving one or more of the satellite signals and providing a received signal, at least one of the low noise blocks receiving a plurality of the satellite signals; and a satellite signal processing unit including a plurality of branches each arranged to receive a corresponding one of the received signals from the plurality of low noise blocks, each branch having a multiplier arranged to weight the received signal by multiplying by a corresponding coefficient; and an adder arranged to add the weighted signals of each branch to generate an output satellite signal.Type: GrantFiled: October 12, 2010Date of Patent: June 17, 2014Assignee: STMicroelectronics S.A.Inventor: Pierre Busson
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Publication number: 20140151561Abstract: A pixel circuit including: a detection circuit having first and second transistors coupled in series between differential output nodes of an antenna, wherein the antenna is configured to be sensitive to terahertz radiation; a capacitor coupled to an intermediate node between the first and second transistors; and control circuitry coupled to control nodes of the first and second transistors, the control circuitry being configured for selectively applying to the control nodes one of: a gate biasing voltage for biasing the control nodes of the first and second transistors during a detection phase of the pixel circuit; and a reset voltage for resetting a voltage stored by the capacitor.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: STMicroelectronics S.A.Inventors: Hani Sherry, Andreia Cathelin
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Patent number: 8745107Abstract: A method for protecting an integrated circuit. According to the method, the start-up of all, or part, of the circuit is determined in the presence of a key which is recorded in a non-volatile manner in the circuit, following the production thereof, and depends on at least one first parameter which is present in a non-volatile manner in the circuit after the production thereof.Type: GrantFiled: September 27, 2005Date of Patent: June 3, 2014Assignee: STMicroelectronics S.A.Inventors: Luc Wuidart, Fabrice Marinet
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Patent number: 8741704Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.Type: GrantFiled: May 18, 2012Date of Patent: June 3, 2014Assignees: International Business Machines Corporation, STMicroelectronics S.A.Inventors: Erwan Dornel, Pascal R. Tannhof, Denis Rideau
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Patent number: 8738919Abstract: A method for recording at least one information block in a first volatile memory external to a circuit, a first digital signature being calculated based on information and data internal to the circuit and a second digital signature being calculated based on first signatures of a group of information blocks and on a digital quantity internal to the circuit and assigned to said group. A method for checking the content of an information block recorded by this recording method.Type: GrantFiled: April 18, 2008Date of Patent: May 27, 2014Assignee: STMicroelectronics S.A.Inventor: Michel Bardouillet
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Patent number: 8735208Abstract: A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) forming, from the front surface of the substrate, areas of same conductivity type as the substrate but of higher doping level, extending deep under the front surface, these areas being bordered with insulating regions orthogonal to the front surface; b) thinning the substrate from the rear surface to the vicinity of these areas and all the way to the insulating regions; c) partially hollowing out the insulating regions on the rear to surface side; and d) performing a laser surface anneal of the rear surface of the substrate.Type: GrantFiled: April 12, 2012Date of Patent: May 27, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: François Roy, Michel Marty
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Patent number: 8722471Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.Type: GrantFiled: January 23, 2013Date of Patent: May 13, 2014Assignees: STMicroelectronics S.A., Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Perrine Batude, Yves Morand
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Patent number: 8716843Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.Type: GrantFiled: April 25, 2012Date of Patent: May 6, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader, Frederic Diette
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Patent number: 8711024Abstract: A switched capacitor amplifier having an amplification unit adapted to amplify a differential signal; a first switched capacitor block including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block including a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase.Type: GrantFiled: June 22, 2009Date of Patent: April 29, 2014Assignee: STMicroelectronics S.A.Inventors: Marc Sabut, Hugo Gicquel, Fabien Reaute, François Van Zanten
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Patent number: 8711954Abstract: A method and a system for transferring a digital signal through a transformer, in which the current in a primary winding of the transformer is a frequency-modulated signal exhibiting sinusoidal trains of different durations according to the rising or falling edge of the digital signal to be transferred.Type: GrantFiled: December 28, 2007Date of Patent: April 29, 2014Assignee: STMicroelectronics S.A.Inventors: Arnaud Florence, Jerome Heurtier
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Patent number: 8704282Abstract: A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) thinning the substrate from its rear surface; b) depositing, on the rear surface of the thinned substrate, an amorphous silicon layer of same conductivity type as the substrate but of higher doping level; and c) annealing at a temperature enabling to recrystallized the amorphous silicon to stabilize it.Type: GrantFiled: April 12, 2012Date of Patent: April 22, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Michel Marty, François Roy, Jens Prima
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Patent number: 8704358Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 ?m, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.Type: GrantFiled: November 28, 2012Date of Patent: April 22, 2014Assignee: STMicroelectronics S.A.Inventors: Pierre Bar, Sylvain Joblot, Nicolas Hotellier
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Patent number: 8703528Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.Type: GrantFiled: April 12, 2012Date of Patent: April 22, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Michel Marty, François Roy, Jens Prima
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Patent number: 8704363Abstract: An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple.Type: GrantFiled: October 22, 2010Date of Patent: April 22, 2014Assignee: STMicroelectronics S.A.Inventors: Yacine Felk, Alexis Farcy
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Publication number: 20140103972Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.Type: ApplicationFiled: October 9, 2013Publication date: April 17, 2014Applicants: MentorGraphics Corporation, STMicroelectronics S.A.Inventors: Anna Asquini, Vincent Vallet
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Patent number: 8693562Abstract: A process receives a composite signal transmitted via a nonlinear data transmission channel, with the composite signal having a first signal UL and a second signal LL. The process includes the following: demodulating and decoding the first signal UL by using a first demodulation and decoding chain in order to regenerate first information of the first signal UL; recoding and shaping to produce a continuous time waveform; applying a nonlinearity function based on a set of coefficients updated according to an adaptive correlation calculation process to the continuous time waveform; subtracting the result of the nonlinearity function from the composite signal in order to generate a result E; and demodulating and decoding the result E by using a second demodulation and decoding chain in order to regenerate second information of the second signal LL.Type: GrantFiled: May 13, 2004Date of Patent: April 8, 2014Assignee: STMicroelectronics S.A.Inventor: Jacques Meyer
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Publication number: 20140061723Abstract: A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.Type: ApplicationFiled: September 3, 2013Publication date: March 6, 2014Applicant: STMicroelectronics S.A.Inventor: Vincent Quenette
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Patent number: 8665038Abstract: A filtering circuit with BAW type acoustic resonators having at least a first quadripole and a second quadripole connected in cascade, each quadripole having a branch series with a first acoustic resonator of type BAW and a branch parallel with each branch having an acoustic resonator of type BAW, the first acoustic resonator having a frequency of resonance series approximately equal to the frequency of parallel resonance of the second acoustic resonator, the branch parallel of the first quadripole having a first capacitance connected in series with the second resonator and, in parallel with the capacitance, a first switching transistor to short circuit the capacitance.Type: GrantFiled: February 13, 2009Date of Patent: March 4, 2014Assignees: STMicroelectronics S.A., Centre National de la Recherche ScientifiqueInventors: Didier Belot, Alexandre Augusto Shirakawa, Eric Kerherve, Moustapha El Hassan, Yann Deval
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Patent number: 8659465Abstract: A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal.Type: GrantFiled: November 10, 2011Date of Patent: February 25, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Grenoble 2) SASInventors: Laurent Simony, Benoît Deschamps, Alexandre Cellier, Frédéric Barbier