Patents Assigned to STMicroelectronic S.A.
  • Patent number: 8554813
    Abstract: A method and a circuit for detecting a loss in the equiprobable character of a first output bit flow originating from at least one first element of normalization of an initial bit flow, including analyzing the flow rate of the normalization element.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: October 8, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre-Yvan Liardet, Yannick Teglia
  • Patent number: 8531261
    Abstract: Method for improving the symmetry of the differential output signals of an integrated transformer of the symmetric-asymmetric type comprising an inductive primary circuit and an inductive secondary circuit, characterized in that the capacitive coupling between the primary and secondary circuits is reduced.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 10, 2013
    Assignee: STMicroelectronics, S.A.
    Inventors: Denis Pache, Nejdat Demirel
  • Patent number: 8524522
    Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 3, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Michel Marty, Didier Dutartre, Francois Roy, Pascal Besson, Jens Prima
  • Patent number: 8528096
    Abstract: A secure Universal Serial Bus (USB) storage device includes a memory controller capable of storing data in and retrieving data from a memory. The secure USB storage device also includes a USB secure microcontroller capable of authorizing access to the memory through the memory controller to thereby secure the memory. The USB secure microcontroller is also capable of protecting the data stored in the memory to thereby secure contents of the memory. The USB secure microcontroller could include an SPI interface and/or a GPIO interface emulating one or more of an SPI interface and an MMC interface to the memory controller. The memory controller could include an SPI interface and/or an MMC interface to the USB secure microcontroller. The secure USB storage device may be enumerated by a USB host controller under one or more device classes.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: September 3, 2013
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.A.
    Inventors: Serge F. Fruhauf, Jerome Tournemille
  • Patent number: 8519806
    Abstract: A method for forming a resonator including a resonant element, the resonant element being at least partly formed of a body at least partly formed of a first conductive material, the body including open cavities, this method including the steps of measuring the resonator frequency; and at least partially filling said cavities.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: August 27, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Fabrice Casset, Cédric Durand
  • Patent number: 8514083
    Abstract: The invention concerns an inductive element for forming an electromagnetic transponder antenna, comprising a first group of mutually parallel conductors coplanar in a first plane, a second group of mutually parallel conductors coplanar in a second plane parallel to the first plane, and an insulating material separating the two groups of conductors, one end of each conductor of the first group being connected to one end of a conductor of the second group whereof the other end is connected to one end of another conductor of the first group, the connections between the conductors being conductive via holes in the thickness of the insulating material.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: August 20, 2013
    Assignee: STMicroelectronics S.A.
    Inventor: Christophe Mani
  • Patent number: 8514123
    Abstract: A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: August 20, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Stéphane Le Tual, Mounir Boulemnakher, Pratap Narayan Singh
  • Patent number: 8504892
    Abstract: A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: August 6, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Vincent Heinrich, Laurent Paumier
  • Publication number: 20130193550
    Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.
    Type: Application
    Filed: January 28, 2013
    Publication date: August 1, 2013
    Applicants: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics S.A.
    Inventors: STMicroelectronics S.A., Commissariat a l'Energie Atomique et aux Energies Alternatives
  • Publication number: 20130196500
    Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.
    Type: Application
    Filed: January 23, 2013
    Publication date: August 1, 2013
    Applicants: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics S.A.
    Inventors: STMicroelectronics S.A., Commissariat a l'Energie Atomique et aux Energies Alternatives
  • Patent number: 8497795
    Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plu
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: July 30, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics Pvt. Ltd., STMicroelectronics (Canada) Inc., STMicroelectronics S.r.l.
    Inventors: Stéphane Le Tual, Pratap Narayan Singh, Oleksiy Zabroda, Nicola Vannucci
  • Patent number: 8493293
    Abstract: This invention relates to systems, methods and apparatus for driving organic light emitting diodes (OLED) displays, in particular those using multi-line addressing (MLA) techniques. Embodiments of the invention are particularly suitable for use with so-called passive matrix OLED displays. A current drive system for an electroluminescent display, the system comprising: a plurality of current mirrors having a plurality of outputs for driving a plurality of drive electrodes of said display, each said current mirror having a reference signal input; and an automatic selector coupled to said current mirror outputs to automatically select a said output for providing reference signal inputs to said current mirrors.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: July 23, 2013
    Assignees: Cambridge Display Technology Limited, STMicroelectronics S.A.
    Inventors: Paul Richard Routley, Olivier Le-Briz
  • Publication number: 20130181784
    Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 18, 2013
    Applicants: International Business Machines Corporation, STMicroelectronics S.A.
    Inventors: STMicroelectronics S.A., International Business Machines Corporation
  • Publication number: 20130181785
    Abstract: A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 18, 2013
    Applicants: International Business Machines Corporation, STMicroelectronics S.A.
    Inventors: STMicroelectronics S.A., International Business Machines Corporation
  • Patent number: 8486817
    Abstract: A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: July 16, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergies Atomique et aux Énergies Alternatives
    Inventors: Perceval Coudrain, Philippe Coronel, Nicolas Buffet
  • Patent number: 8470190
    Abstract: A method for processing at least one wall of an opening formed in a silicon substrate, successively including the steps of implanting fluorine atoms into an upper portion of the wall of the opening, performing an oxidization step, and applying a specific processing to at least a portion of the non-implanted portion of the opening.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Edgard Jeanne, Sylvain Nizou
  • Publication number: 20130155283
    Abstract: An image sensor including a pixel array, each pixel including, in a substrate of a doped semiconductor material of a first conductivity type, a first doped region of a second conductivity type at the surface of the substrate; an insulating trench surrounding the first region; a second doped region of the first conductivity type, more heavily doped than the substrate, at the surface of the substrate and surrounding the trench; a third doped region of the second conductivity type, forming with the substrate a photodiode junction, extending in depth into the substrate under the first and second regions and being connected to the first region; and a fourth region, more lightly doped than the second and third regions, interposed between the second and third regions and in contact with the first region and/or with the third region.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 20, 2013
    Applicants: STMicroelectronics (Crolles2) SAS, STMicroelectronics S.A.
    Inventors: STMicroelectronics S.A., STMicroelectronics (Crolles2) SAS
  • Patent number: 8461941
    Abstract: A bulk acoustic wave resonator has an adjustable resonance frequency. A piezoelectric element is provided having first and second electrodes. A switching element is provided in the form of a MEMS structure which is deformable between a first and second position. The switching element forms an additional electrode that is selectively disposed on top of, and in contact with, one of the first and second electrodes. This causes a total thickness of the electrode of the resonator to be changed resulting in a modification of the resonance frequency of the resonator.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: June 11, 2013
    Assignees: STMicroelectronics S.A., Centre National de la Recherche Scientifique
    Inventors: Didier Belot, Andréia Cathelin, Yann Deval, Moustapha El Hassan, Eric Kerherve, Alexandre Shirakawa
  • Publication number: 20130140693
    Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 ?m, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.
    Type: Application
    Filed: November 28, 2012
    Publication date: June 6, 2013
    Applicant: STMicroelectronics S.A.
    Inventor: STMicroelectronics S.A.
  • Patent number: 8456258
    Abstract: A resonant device including a stack of a first metal layer, a piezoelectric material layer, and a second metal layer formed on a silicon substrate, a cavity being formed in depth in the substrate, the thickness of the silicon above the cavity having at least a first value in a first region located opposite to the center of the stack, having a second value in a second region located under the periphery of the stack and having at least a third value in a third region surrounding the second region, the second value being greater than the first and the third values.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Perceval Coudrain, David Petit