Abstract: A photonic integrated device includes a first waveguide and a second waveguide. The first and second waveguides are mutually coupled at a junction region which includes a bulge region. The bulge region is defined two successive etching operations using two distinct etch masks, where the first etching operation is a partial etch and the second etching operation is a complete etch.

Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.

Abstract: An optical pulse emitter includes a light emitting device having a first node coupled to an intermediate node via a first switch. The intermediate node is coupled to a supply voltage node via a second switch. A capacitor is coupled to the intermediate node. The first, second and third switches are controlled by a control circuit. During a first phase, the second switch is actuated to couple the capacitor to the supply voltage node. During a second phase, the second switch is deactuated and the first switch is actuated to at least partially discharge the capacitor through the light emitting device. During a third phase, discharge current from the capacitor bypasses around the light emitting device.

Abstract: A main carrier wafer includes a first integrated network of electronic connections between front and back faces. A first electronic chip is mounted to the front face of the main carrier wafer and connected to the network of electronic connections of the main carrier wafer. A secondary carrier wafer includes a platform that extends over the first chip and a base the protrudes backwards with respect to the platform to a back end face facing the main wafer. A second integrated network of electronic connections is provided within the secondary carrier wafer. A second electronic chip is mounted on top of the platform and connected to the second integrated network. The second integrated network is further connected to the main carrier wafer at the back end face.

Abstract: An electronic module includes an ambient light sensor and a proximity sensor. The ambient light sensor includes an ambient light photodetector. The proximity sensor includes an infrared photoemitter, a reference infrared photodetector and another infrared photodetector. The ambient light sensor is arranged in a stack over the proximity sensor with a position that allows infrared photons transmitted by the infrared photoemitter to be received by the reference infrared photodetector.

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.

Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

Abstract: A carrier wafer has a back face and a front face and a network of electrical connections between the back face and the front face. A first electronic chip is mounted with its bottom face on top of the front face of the carrier wafer. The first electronic chip has a through-opening extending between the bottom face and a face. A second electronic chip is installed in the through-opening and mounted to the front face of the carrier wafer.

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.

Abstract: A voltage regulator includes two input pairs of opposite type transistors, p-type and n-type, to provide a soft-start functionality for gradually increasing the voltage regulator's output voltage from zero, or a voltage below the thresholds of the n-type transistors, to an operational voltage. The voltage regulator operates in a soft-start mode during which a variable input voltage signal is ramped up to allow the output voltage to reach the operational voltage, and a normal-operation mode during which the operational voltage is maintained.

Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.

Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.

Abstract: A control circuit controls the operation of a brushless DC (BLDC) sensorless motor having a first terminal connected to a first winding, a second terminal connected to a second winding and a third terminal connected to a third winding. A driver circuit applies drive signals to the first and second terminals and places the third terminal in a high-impedance state. The drive signals include first drive signals at a first current amplitude and second drive signals at a second, different, current amplitude. A differencing circuit senses a first mutual inductance voltage at the third terminal in response to the first drive signals and senses a second mutual inductance voltage at the third terminal in response to the second drive signals. The differencing circuit further determines a difference between the first and second mutual inductance voltages and produces a difference signal that is used for zero-crossing detection and rotor position sensing.

Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

Abstract: A MEMS gyroscope, wherein a suspended mass is mobile with respect to a supporting structure. The mobile mass is affected by quadrature error caused by a quadrature moment; a driving structure is coupled to the suspended mass for controlling the movement of the mobile mass in a driving direction at a driving frequency. Motion-sensing electrodes, coupled to the mobile mass, detect the movement of the mobile mass in the sensing direction and quadrature-compensation electrodes are coupled to the mobile mass to generate a compensation moment opposite to the quadrature moment. The gyroscope is configured to bias the quadrature-compensation electrodes with a compensation voltage so that the difference between the resonance frequency of the mobile mass and the driving frequency has a preset frequency-mismatch value.

Abstract: A level-shifter circuit operates to shift an input signal referenced to a first set supply voltages to generate an output signal referenced to a second set of supply voltages. The output signal from the level-shifter circuit is latched by a latching circuit. A logic gate has a first input configured to receive the input signal, a second input configured to receive a feedback signal and an output coupled to a input of the level shifting circuit. A feedback circuit has a first input configured to receive the output signal, a second input configured to receive the input signal and an output configured to generate the feedback signal. The feedback circuit operates to sense an uncontrolled switching event of the output signal occurring in the absence of a switching of the input signal and apply, in response thereto, the feedback signal to cancel the uncontrolled switching event.

Abstract: First and second video frames in a flow of digital video frames are encoded by extracting respective sets of keypoints and descriptors, each descriptor including a plurality of orientation histograms regarding a patch of pixels centered on the respective keypoint. Once a pair of linked descriptors has been identified, one for each frame, which have a minimum distance from among the distances between any one of the descriptors of the first frame and any one of the descriptors of the second frame, the differences of the histograms of the descriptors linked in the pair are calculated, and the descriptors linked in the pair are encoded as the set including one of the linked descriptors and the histogram differences by subjecting the histogram differences to a thesholding setting at zero all the differences below a certain threshold, to quantization, and to run-length encoding.

Abstract: The method of determination of a depth map of a scene comprises generation of a distance map of the scene obtained by time of flight measurements, acquisition of two images of the scene from two different viewpoints, and stereoscopic processing of the two images taking into account the distance map. The generation of the distance map includes generation of distance histograms acquisition zone by acquisition zone of the scene, and the stereoscopic processing includes, for each region of the depth map corresponding to an acquisition zone, elementary processing taking into account the corresponding histogram.

Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.