Patents Assigned to STMicroelectronics AS
-
Patent number: 10447345Abstract: An embodiment near-field communication (NFC) router, includes a first switch coupled between a first terminal of the NFC router and a second terminal of the NFC router; and a rectifier bridge having an output terminal coupled to a control terminal of the first switch, the rectifier bridge being configured to rectify a signal detected by an antenna external to the NFC router.Type: GrantFiled: December 12, 2018Date of Patent: October 15, 2019Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: Nathalie Vallespin
-
Patent number: 10447138Abstract: A converter configured to convert a DC input voltage to a DC output voltage, may include: a high-side driver circuit having a first terminal coupled to a first die pad; a high-side transistor having a drain terminal coupled to a second die pad and a source terminal coupled to a third die pad; and a low-side transistor having a source terminal coupled to a fourth die pad and a drain terminal coupled to a fifth die pad. The converter may further include a resistive element coupled between the source terminal of the high-side transistor and the drain terminal of the low-side transistor, where a second terminal of the high-side driver circuit is coupled to a sixth die pad.Type: GrantFiled: March 28, 2017Date of Patent: October 15, 2019Assignee: STMICROELECTRONICS S.R.L.Inventors: Alberto Riva, Giorgio Oddone
-
Patent number: 10444899Abstract: A touch screen controller includes input circuitry receiving touch data from a touch screen, and processing circuitry. The processing circuitry determines first coordinates of a touch at a first time, based upon the received touch data. A first threshold window is set about the first coordinates, with the first threshold window having a central point at the first coordinates, and a second threshold window is set about the first coordinates, with the second threshold window having a central point at the first coordinates and being larger than the first threshold window. Second coordinates of the touch are determined at a second time, based upon the received touch data, and where the second coordinates are not within the first threshold window but are within the second threshold window, the second coordinates are corrected based upon a distance between the second coordinates and the central point of the second threshold window.Type: GrantFiled: January 23, 2017Date of Patent: October 15, 2019Assignee: STMicroelectronics Asia Pacific Pte LtdInventor: Manivannan Ponnarasu
-
Patent number: 10445068Abstract: An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.Type: GrantFiled: September 14, 2018Date of Patent: October 15, 2019Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Patrick Haddad, Viktor Fischer
-
Patent number: 10447230Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.Type: GrantFiled: July 18, 2017Date of Patent: October 15, 2019Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Frédéric Gianesello, Romain Pilard, Cédric Durand
-
Patent number: 10446235Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.Type: GrantFiled: May 21, 2018Date of Patent: October 15, 2019Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: François Tailliet
-
Patent number: 10444264Abstract: A device measures the current in an inductive load using two separate current-measuring paths to detect the current in the inductive load. The inductive load is connected between first and second nodes, and the first node connected to a first voltage. The device includes first and second transistors cascaded together between the first node and a third node that is connected to a second voltage. First and second sense amplifiers measure the current in the inductive load. The first and second sense amplifiers are connected to at least one terminal of the first and second transistors. Two blocks sample and hold signals from the first and second sense amplifiers, which represent, respectively, the currents in the two separate current-measuring paths. The two currents are subtracted in a comparison node for generating an error signal that is compared with a predefined window and if outside the window a failure signal is generated.Type: GrantFiled: January 30, 2019Date of Patent: October 15, 2019Assignee: STMicroelectronics S.r.l.Inventors: Vanni Poletto, Riccardo Miglierina, Antonio Davide Leone, Sergio Lecce
-
Patent number: 10447145Abstract: In an embodiment, a method for soft-starting an SMPS includes: asserting an enable signal; disabling an output stage of the SMPS; after asserting the enable signal, measuring a feedback voltage of the SMPS; receiving a first reference voltage at an input reference node; comparing the measured feedback voltage with the first reference voltage; and, when the measured feedback voltage is lower than the first reference voltage, storing the feedback voltage in a soft-start capacitor, connecting an output reference node to the soft-start capacitor, enabling the output stage of the SMPS, and switching a transistor of the output stage to regulate the output voltage based on the feedback voltage and a second reference voltage at the output reference node, and injecting a current into the soft-start capacitor.Type: GrantFiled: November 19, 2018Date of Patent: October 15, 2019Assignee: STMicroelectronics (Grenoble 2) SASInventors: Danika Perrin, Valerie Carrat, Marc Sabut
-
Patent number: 10441972Abstract: A transmission channel transmits high-voltage pulses in a transmission phase and receives echoes of the high-voltage pulses in a receiving phase. The transmission channel includes a buffer with anti-memory circuitry to couple drain conduction terminals of buffer transistors of a high-side of a buffer of the transmission channel to a low-side reference voltage of a low-side of the buffer and couple drain conduction terminals of buffer transistors of the low-side of the buffer to a high-side reference voltage of the high-side of the buffer during the clamping phase.Type: GrantFiled: July 26, 2016Date of Patent: October 15, 2019Assignee: STMicroelectronics S.r.l.Inventors: Davide Ugo Ghisu, Sandro Rossi, Dario Bianchi
-
Publication number: 20190312039Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.Type: ApplicationFiled: April 9, 2019Publication date: October 10, 2019Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SASInventors: Francois Andrieu, Remy Berthelon, Bastien Giraud
-
Publication number: 20190312575Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.Type: ApplicationFiled: January 22, 2019Publication date: October 10, 2019Applicant: STMicroelectronics International N.V.Inventors: Manoj Kumar Kumar TIWARI, Saiyid Mohammad Irshad RIZVI
-
Publication number: 20190312170Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.Type: ApplicationFiled: December 17, 2018Publication date: October 10, 2019Applicant: STMicroelectronics (Crolles 2) SASInventor: Francois ROY
-
Publication number: 20190310736Abstract: Disclosed is a method for testing touch screen displays during manufacture. A touch screen controller (TSC) is packaged, and the analog channels of the TSC are characterized, with resulting data being stored for later use. The TSC is programmed, and the touch screen display and TSC are packaged together. The touch screen display is tested using firmware in the TSC, enabling calculation of the inherent capacitances between force and sense lines of the touch screen display when connected to the TSC during operation. The testing involves, for each force and sense line pair, measuring an output signal generated by a receive channel of the TSC coupled to the sense line of that pair. Based upon the data gathered during characterization, and the signals measured during testing, the capacity of the touch screen display is then calculated.Type: ApplicationFiled: April 9, 2018Publication date: October 10, 2019Applicant: STMicroelectronics Design and Application S.R.O.Inventors: Milan ANDRLE, Martin HAVLASEK, Martin FUCIK
-
Publication number: 20190310467Abstract: A projector includes a mirror quasi-statically driven by a drive signal to scan a laser beam in a pattern. A drive circuit generates the drive signal so the mirror moves in a non-linear fashion, yielding unwanted resonances. The non-linearity results in movement of the mirror through a first projection area, into a dead zone, and into a second projection area. The laser beam is emitted as the mirror moves through the first and second projection areas, but not the dead zone. A controller samples a feedback signal of the mirror as it moves through the first and second projection areas, producing first and second projection area sample which are processed to produce first and second ripple measurements. First and second correction signals are generated as a function of the ripple measurements. The drive circuit applies the correction signals to the drive signal so that the unwanted resonances are attenuated.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Applicant: STMicroelectronics LTDInventor: Avi RESLER
-
Patent number: 10436881Abstract: A method may include generating, within a device, separate and discrete wavelengths, and generating light intensity profiles based on an interaction between the separate and discrete wavelengths and a multi-wavelength diffractive optic element. The method may include detecting an object from light reflected from the object using the light intensity profiles. The light intensity profiles may include a shorter range light intensity profile and a longer range light intensity profile, each light intensity profile having different energy per solid angle patterns.Type: GrantFiled: February 29, 2016Date of Patent: October 8, 2019Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITEDInventors: James Peter Drummond Downing, Adam Caley
-
Patent number: 10439569Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.Type: GrantFiled: May 21, 2018Date of Patent: October 8, 2019Assignee: STMicroelectronics S.r.l.Inventors: Stefano Ramorini, Alberto Cattani, Germano Nicollini, Alessandro Gasparini
-
Patent number: 10434252Abstract: A flow rate sensor is provided in a wireless, leadless package. The flow rate sensor includes a MEMs sensor coupled to an ASIC and an antenna. The flow rate sensor is powered by radiation received from a control module adjacent the flow rate sensor. The flow rate sensor is placed within a fluid and monitors the flow rate of the fluid. The control module is not in the fluid and receives flow rate data from the flow rate sensor.Type: GrantFiled: December 29, 2015Date of Patent: October 8, 2019Assignee: STMicroelectronics, Inc.Inventors: Nicholas Trombly, Patrick Furlan
-
Patent number: 10437558Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.Type: GrantFiled: August 28, 2018Date of Patent: October 8, 2019Assignee: STMicroelectronics S.r.l.Inventors: David Vincenzoni, Samuele Raffaelli
-
Patent number: 10439439Abstract: A device includes a first module having an electromagnetic loudspeaker having an inductive element configured to drive a membrane of the electromagnetic loudspeaker. A second module is coupled between the inductive element and a load. The second module is configured to carry out a contactless transfer of energy from an emitter to the load via the inductive element.Type: GrantFiled: August 31, 2017Date of Patent: October 8, 2019Assignee: STMicroelectronics (Grand Ouest) SASInventor: Lionel Cimaz
-
Patent number: 10438856Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.Type: GrantFiled: April 3, 2013Date of Patent: October 8, 2019Assignee: STMICROELECTRONICS, INC.Inventors: John H. Zhang, Chengyu Niu, Heng Yang