Patents Assigned to STMicroelectronics AS
  • Publication number: 20190285694
    Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 19, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent HUARD, Chittoor PARTHASARATHY
  • Publication number: 20190285196
    Abstract: A valve module includes a semiconductor body, cavities in the semiconductor body separated from each other by a distance, a cantilever structure suspended over each cavity to enable at least partial closing of the cavity, and a piezoelectric actuator for each cantilever structure. The piezoelectric actuator is configured for use to cause a positive bending of the respective cantilever structure and so modulate a rate of air flow through the valve module.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 19, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventors: Domenico GIUSTI, Oriana Rita Antonia DI MARCO, Igor VARISCO
  • Publication number: 20190287874
    Abstract: An electronic device includes a carrier wafer having a front side and a back side, with an electrical connection network configured to connect the front side to the back side. An electronic chip is mounted on the front side of the carrier wafer and electrically connected to front pads of the electrical connection network. A sheet of a thermally conductive graphite or a pyrolytic graphite is added to the back side of the carrier wafer. The sheet includes apertures which leave back pads of the electrical connection network uncovered.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 19, 2019
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Didier CAMPOS
  • Patent number: 10418095
    Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Abhishek Pathak
  • Patent number: 10418987
    Abstract: A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics KK
    Inventors: Luca Bartolomeo, Kazuo Eguchi, Giuseppe Davide Bruno
  • Patent number: 10418982
    Abstract: A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Beng-Heng Goh
  • Patent number: 10416142
    Abstract: An optoelectronic device for detecting volatile organic compounds is described, including a die with a semiconductor body, the die forming a MOSFET transistor and at least one photodiode. The optoelectronic device is optically couplable to an optical source that emits radiation with a spectrum at least partially overlapping the absorption spectrum range of the semiconductor body. The MOSFET transistor is planar and includes a gate region and a catalytic region that is arranged on the gate region such that, in the presence of a gas mixture including volatile organic compounds, the MOSFET transistor can be biased to generate an electrical signal indicating the overall concentration of the gas mixture. The photodiode generates a photocurrent that is a function of the concentration of one or more polycyclic aromatic hydrocarbons present in the gas mixture.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: September 17, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Antonella Sciuto
  • Patent number: 10418660
    Abstract: In manufacturing a lithium battery, a plasma deposition of a layer of LiPON is made on a structure that includes an anode contact zone and a cathode contact zone. Before making the deposition of layer of LiPON, a conductive portion is deposited to short the anode contact zone to the cathode contact zone. After the deposition of the layer of LiPON in completed, the conductive portion is cut to sever the short between the anode and cathode contact zones.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Julien Ladroue, Fabien Pierre
  • Patent number: 10416802
    Abstract: Disclosed is a touch sensor and method for detecting a touch in a capacitive touchscreen application, wherein the touch sensor is capable of distinguishing between a finger hovering above the touch sensor and a touch from a stylus having a small contact surface area without having to adjust the sensitivity of the touch sensor. The touch sensor includes a first sensing electrode, a transmit electrode, and a second sensing electrode, wherein the second sensing electrode is positioned substantially around the perimeter of the inner circuitry (i.e., transmit electrode and first sensing electrode). A touch is detected by sensing changes in a first capacitance between the transmit electrode and first sensing electrode and a second capacitance between the transmit electrode and second sensing electrode. The changes in the first and second capacitances are compared to determine whether the changes in the capacitances are due to a finger hover or a touch.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Praveesh Chandran, Gee-Heng Loh, Ravi Bhatia, Ys On
  • Patent number: 10418322
    Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Patrick Regnier
  • Patent number: 10417364
    Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 17, 2019
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Thomas Boesch, Giuseppe Desoli
  • Patent number: 10418486
    Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 17, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Francois Andrieu
  • Patent number: 10418402
    Abstract: In an embodiment, an image sensor includes a semiconductor substrate, an epitaxial layer disposed over the semiconductor substrate, a first heavily doped region disposed in the epitaxial layer, and a shallow trench isolation region disposed in the epitaxial layer and surrounding the first heavily doped region. The semiconductor substrate and the epitaxial layer are of a first doping type and the semiconductor substrate is coupled to a reference potential node. The first heavily doped region is of a second doping type opposite to the first doping type. The epitaxial layer, the first heavily doped region, and the shallow trench isolation region are part of a p-n junction photodiode configured to operate in the near ultraviolet region.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Jeffrey M. Raynor
  • Patent number: 10416294
    Abstract: A ranging device includes an array of photon detection devices that receive an optical signal reflected by an object in an image scene and first and second logic devices to respectively combine the outputs of first and second pluralities of the photon detection devices. First and second counter circuits are respectively coupled an output of the first and second logic devices and generate first and second count values respectively by counting the photon detection events generated by the first and second pluralities of photon detection devices. A range estimation circuit estimates the range of the object by estimating the timing of one or more pulses of said optical signal based on the first and second count values.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 17, 2019
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Genoble 2) SAS
    Inventors: Pascal Mellot, Stuart McLeod, Marc Drader
  • Patent number: 10420140
    Abstract: Multicast transmissions are efficient but do not allow for individual acknowledgement that the data was received by each receiver. This is not acceptable for isochronous systems that require specific levels of QoS for each device. A multimedia communications protocol is provided that uses a novel multi-destination burst transmission protocol in multimedia isochronous systems. The transmitter establishes a bi-directional burst mode for multicasting data to multiple devices and receiving Reverse Start of Frame (RSOF) delimiters from each multicast-destination receiver in response to multiple SOF delimiters, thus providing protocol-efficient multi-destination acknowledgements.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Oleg Logvinov, Aidan Cully, David Lawrence, Michael J. Macaluso
  • Patent number: 10419058
    Abstract: A contactless component, connected to an antenna, includes a plurality of terminals and a first, second, third, and fourth plurality of switchable auxiliary capacitors. The plurality of terminals include a first output terminal, a second output terminal, a first auxiliary terminal, and a second auxiliary terminal. Each of the first plurality of switchable auxiliary capacitors is connected between the first auxiliary terminal and the first output terminal. Each of the second plurality of switchable auxiliary capacitors is coupled between the first auxiliary terminal and a neutral point. Each of the third plurality of switchable auxiliary capacitors is coupled between the second auxiliary terminal and the second output terminal of the contactless component. Each of the fourth plurality of switchable auxiliary capacitors is coupled between the second auxiliary terminal and the neutral point.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Alexandre Tramoni
  • Patent number: 10416702
    Abstract: A first current proportional to absolute temperature flows in a first current line through a first p-n junction and a second p-n junction arranged in series. A cascaded arrangement of p-n junctions is coupled to the second p-n junction and includes a further p-n junction with a current flowing therethrough that has a third order proportionality on absolute temperature. A differential circuit has a first input coupled to the further p-n junction and a second input coupled to a current mirror from the first p-n junction, with the differential circuit configured to generate a bandgap voltage with a low temperature drift from a sum of first voltage (that is PTAT) derived from the first current and a second voltage (that is PTAT3) derived from the third current.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronic S.r.l.
    Inventors: Germano Nicollini, Stefano Polesel
  • Patent number: 10419434
    Abstract: A device protects an incoming multimedia signal with a protection that is controllable and configured for enabling or disabling an application for an interface protection on an outgoing signal coming from the incoming signal. An output interface is configured for delivering the outgoing signal on an output. An authorization process is performed for authorizing or otherwise a control over the enabling or disabling of the interface protection application depending on security rules.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics SA
    Inventor: Jocelyn Leheup
  • Patent number: 10419432
    Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: September 17, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble2) SAS, STMicroelectronics S.R.L.
    Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Hajer Ferjani, Giuseppe Maruccia, Raffaele Guarrasi, Giuseppe Guarnaccia
  • Patent number: 10418488
    Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: Pierre Morin