Abstract: An integrated MEMS structure includes a driving assembly anchored to a substrate and actuated with a driving movement. A pair of sensing masses suspended above the substrate and coupled to the driving assembly via elastic elements is fixed in the driving movement and performs a movement along a first direction of detection, in response to an external stress. A coupling assembly couples the pair of sensing masses mechanically to couple the vibration modes. The coupling assembly is formed by a rigid element, which connects the sensing masses and has a point of constraint in an intermediate position between the sensing masses, and elastic coupling elements for coupling the rigid element to the sensing masses to present a first stiffness to a movement in phase-opposition and a second stiffness, greater than the first, to a movement in phase, of the sensing masses along the direction of detection.

Abstract: A device described herein includes a movable MEMS mirror, with a driver configured to drive the movable MEMS mirror with a periodic signal such that the MEMS mirror oscillates at its resonance frequency. A feedback measuring circuit is configured to measure a signal flowing through the movable MEMS mirror. A processor is configured to sample the signal at first and second instants, generate an error signal as a function of a difference between the signal at the first instant in time and the signal at the second instant in time, and determine the opening angle of the movable MEMS mirror as a function of the error signal.

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.

Abstract: First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.

Abstract: A method of controlling a current flowing through a load including the steps of: applying a first transfer function representative of the load to a first voltage to obtain a second voltage; applying the second voltage to a first terminal of a circuit for generating the current; sampling a third voltage between first and second terminals of the load; comparing the third voltage with the second voltage; and determining the current to be supplied to the load according to the result of the comparison.

Abstract: An electronic device disclosed herein includes a linear output stage configured to generate an output voltage to an output node as a function of an input voltage, and a buck output stage configured to generate the output voltage to the output node as a function of the input voltage. Control circuitry is configured to enable the linear output stage and disable the buck output stage if a current demanded by a load to maintain the output voltage at a desired level is less than a limit current, and enable the buck output stage and disable the linear output stage a delay period of time after enabling the buck output stage, if the current demanded by the load to maintain the output voltage at the desired level is greater than the limit current.

Abstract: A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.

Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.

Abstract: A control device controls a switching circuit for a converter. The switching circuit comprises a half-bridge having a high-side transistor and a low-side transistor. The control device comprises a controller configured to control turning on and turning off said two transistors, so that a square-wave voltage is applied to the transformer primary. The controller is configured to start switching the half-bridge by turning on the low-side transistor. The control device comprises a first timer configure to initially turn on the low-side transistor for a duration given by a first time period useful for pre-charging a bootstrap capacitor couplable to the middle point of the half-bridge, and a second timer configured to keep the low-side transistor and the high-side transistor turned off for a second time period immediately following the first time period and having a longer duration than the first time period.

Abstract: A method of forming semiconductor devices, such as capacitive type MEMS acoustic transducers, in a semiconductor includes forming a mask layer on a back surface of the semiconductor wafer and removing first etch portions of the mask layer and scribe trench portions of the mask layer. Each scribe trench portion is positioned in the mask layer to define a corresponding scribe boundary of a plurality of the semiconductor devices being formed in the semiconductor wafer. Etching the semiconductor wafer through the first etch portions and the scribe trench portions may be done simultaneously to form external back chambers and scribe trenches, respectively, in the semiconductor wafer. The semiconductor wafer is then cut along cutting lines in the scribe trenches to singulate individual MEMS acoustic transducers. The etching through the first and second etch portions and the scribe trench portions are dry etching of the semiconductor substrate in one embodiment.

Abstract: A Schottky diode is formed on a silicon support. A non-doped GaN layer overlies the silicon support. An AlGaN layer overlies the non-doped GaN layer. A first metallization forming an ohmic contact and a second metallization forming a Schottky contact are provided in and on the AlGaN layer. First vias extend from the first metallization towards the silicon support. Second vias extend from the second metallization towards an upper surface.

Abstract: A battery charger includes an input supply terminal configured to receive a supply signal and a battery terminal configured to be connected to a battery. A supply switching circuit is arranged between the battery terminal and the input supply terminal. A control device generates a control signal to control operation of the supply switching circuit. A fuel gauge device provide a digital estimation of a voltage signal across the battery. A correction device modifies the control signal in response to the digital estimation of the voltage signal across the battery if that digital estimation is outside of a value range between two thresholds.

Abstract: A packaged device has a die of semiconductor material bonded to a support. An electromagnetic shielding structure surrounds the die and is formed by a grid structure of conductive material extending into the support and an electromagnetic shield, coupled together. A packaging mass embeds both the die and the electromagnetic shield. The electromagnetic shield is formed by a plurality of metal ribbon sections overlying the die and embedded in the packaging mass. Each metal ribbon section has a thickness-to-width ratio between approximately 1:2 and approximately 1:50.

Abstract: System for converting thermal energy into electrical energy (S1) intended to be arranged between a hot source (SC) and a cold source (SF), comprising means for converting thermal energy into mechanical energy (6) and a piezoelectric material, with the means for converting thermal energy into mechanical energy (6) comprising groups (G1, G2) of at least three bimetallic strips (9, 11, 13) linked mechanically together by their longitudinal ends and suspended above a substrate (12), each bimetallic strip (9, 11, 13) comprising two stable states wherein it has in each of the states a curvature, with two directly adjacent bimetallic strips (9, 11, 13) having for a given temperature opposite curvatures, with the switching from one stable state of the bimetallic strips (9, 11, 13) to the other causing the deformation of a piezoelectric material.

Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

Abstract: It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable by the sensed low power electrical signals. It is further recognized that low power devices such as tunneling diodes and TFETs are suitable for use in such biological applications in conjunction with graphene sensors. While tunneling diodes can be used in diagnostic applications, TFETs, which are three-terminal devices, further permit controlling the voltage on one cell according to signals received by other cells. Thus, by the use of a biological sensor system that includes graphene nanowire sensors coupled to a TFET, charge can be redistributed among different biological cells, potentially with therapeutic effects.

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

Abstract: A first capacitor has a capacitance adjustable to a set point value by application of a bias voltage. A second capacitor also has a capacitance adjustable to a set point value by application of a bias voltage. The first and second capacitors are arranged to receive the same bias voltage generated by a control circuit. The control circuit receiving the set point value as an input and generates that bias voltage in response to a quantity representative of a capacitance of the second capacitor.

Abstract: Disclosed herein is a device including a MEMS sensor configured to generate a first differential capacitance representing a change in capacitance from a first original sensing capacitance value and a second differential capacitance representing a change in capacitance from a second original sensing capacitance value, with the first and second original sensing capacitance values being mismatched. A compensation circuit is configured to generate outputs for compensating the first and second differential capacitances for the mismatch. A capacitance to voltage converter receives the first and second differential capacitances and the outputs of the compensation circuit as input and generates an output voltage as a function thereof.