Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

Abstract: A memory cell is manufactured by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) forming a mask on the stack covering only the memory cell location; and (c) etching portions of the stack not covered by the first mask. The formation of the mask covering only the memory cell location comprises defining a first mask extending in a row direction for each row of memory cell locations and then patterning the first mask in a column direction for each column of memory cell locations.

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

Abstract: A semiconductor substrate includes a matrix of photosites. Each photosite is delimited by an isolation trench including polycrystalline silicon. A peripheral zone extends directly around the matrix of photosites. The peripheral zone includes dummy photosites delimited by isolation trenches including polycrystalline silicon. A density of polycrystalline silicon in the peripheral zone is between a density of polycrystalline silicon at an edge of the matrix of photosites and a density of polycrystalline silicon around the peripheral zone.

Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.

Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.

Abstract: A photonic system includes a first photonic circuit having a first face and a second photonic circuit having a second face. The first photonic circuit comprises first wave guides, and, for each first wave guide, a second wave guide covering the first wave guide, the second wave guides being in contact with the first face and placed between the first face and the second face, the first wave guides being located on the side of the first face opposite the second wave guides. The second photonic circuit comprises, for each second wave guide, a third wave guide covering the second wave guide. The first photonic circuit comprises first positioning devices projecting from the first face and the second photonic circuit comprises second positioning devices projecting from the second face, at least one of the first positioning devices abutting one of the second positioning devices in a first direction.

Abstract: Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: The present disclosure relates to a method of making an electronic device comprising a first wafer including at least one trench and a second wafer, the second wafer being bonded, by hybrid bonding, to the first wafer, so as to form, at the level of the trench, at least one enclosed space, empty or gas-filled.

Abstract: An electronic device is provided that includes a photodiode. The photodiode includes a semiconductor region coupled to a node of application of a first voltage, and at least one semiconductor wall. The at least one semiconductor wall extends along at least a height of the photodiode and partially surrounds the semiconductor region.

Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

Abstract: An indirect time-of-flight (iTOF) includes a pixel with a photoconversion area, a readout circuit and at least two circuit sets. Each circuit set includes: a capacitive element connected to a first node of the circuit set; a controllable charge transfer device connected between a first electrode of the photoconversion area and the first node; and a first transistor having a gate connected to the first node, a source connected to the readout circuit and a drain configured to receive a bias potential. The capacitive element is configured to store a voltage in response to charges generated by the photoconversion area.

Abstract: An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.

Abstract: An image sensor includes pixels each including: a first transistor and a first switch that are connected in series between a first node configured to receive a first potential and an internal node of the pixel, a gate of the first transistor being coupled with a floating diffusion node of the pixel; a capacitive element, a first terminal of which is connected to the floating diffusion node of the pixel; and several assemblies each including a capacitance connected in series with a second switch coupling the capacitance to the internal node. The sensor also includes a control circuit configured to control, each time a voltage is stored in one of the assemblies of a pixel, an increase of a determined value of a difference in potential between the floating diffusion node and the internal node of the pixel.

Abstract: A pixel includes a photoconversion zone, an insulated vertical electrode and at least one charge storage zone. The photoconversion zone belongs to a first part of a semiconductor substrate and each charge storage zone belongs to a second part of the substrate physically separated from the first part of the substrate by the insulated vertical electrode.

Abstract: An optical device includes a layer having a face configured to be traversed by light at an operating wavelength. The face of the layer includes a fractal structure lacking rotational symmetry such as a fractal structure that corresponds to a fractal expressed in an L-system. The fractal structure is formed by recesses that penetrate into the layer from the face. The recesses have a depth which is less that a thickness of the layer.