Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Ionizing radiation detector
    Patent number: 11789168
    Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: October 17, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Gilles Gasiot, Fady Abouzeid
  • Image sensor
    Patent number: 11791355
    Abstract: An image sensor is includes a plurality of pixels. Each of the pixels includes a silicon photoconversion region and a material that at least partially surrounds the photoconversion region. The material has a refraction index smaller than the refraction index of silicon, and the interface between the photoconversion region of the pixel and the material is configured so that at least one ray reaching the photoconversion region of the pixel undergoes a total reflection or a plurality of successive total reflections at the interface.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: October 17, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Axel Crocherie
  • STRAINED TRANSISTORS AND PHASE CHANGE MEMORY
    Publication number: 20230329008
    Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Remy BERTHELON, Olivier WEBER
  • INTEGRATED CIRCUIT INCLUDING A METAL PILLAR IN CONTACT WITH A SILICON REGION ON AN OHMIC COUPLING REGION, AND CORRESPONDING MANUFACTURING METHOD
    Publication number: 20230326947
    Abstract: An integrated circuit includes at least one silicon region and at least one metal pillar in contact with the at least one silicon region at an ohmic coupling region. The at least one metal pillar is formed by: depositing a layer of titanium on the at least one silicon region; depositing atomic layers of titanium nitride on the layer of titanium; and annealing at a temperature of between 715° C. and 815° C. for a period of between 5 seconds and 30 seconds. This forms a titanium silicide for the ohmic coupling region in a volume having the appearance of a spherical cap or segment.
    Type: Application
    Filed: April 6, 2023
    Publication date: October 12, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Magali GREGOIRE, Joel SCHMITT
  • Vertical photodiode
    Patent number: 11784275
    Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: October 10, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles Baudot, Sebastien Cremer, Nathalie Vulliet, Denis Pellissier-Tanon
  • IMAGING DEVICE
    Publication number: 20230317748
    Abstract: An imaging device includes an array of photosensors. A film of semiconductor nanoparticles is common to the photosensors of the array. The nanoparticles are configured to be excited by light with wavelengths in a range from 280 to 1500 nanometers. Each photosensor includes a top electrode and a bottom electrode positioned on opposite sides of the film of semiconductor nanoparticles. At least some of the photosensors further include a filter configured to transmit light with wavelengths in a range from 280 to 400 nanometers, and to at least partially filter out light with wavelengths greater than 400 nanometers from reaching the photosensor. A transistor level is electrically coupled to the top and bottom electrodes of the photosensors.
    Type: Application
    Filed: April 3, 2023
    Publication date: October 5, 2023
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Jonathan STECKEL, Emmanuel JOSSE, Eric MAZALEYRAT, Youness RADID
  • PHOTODIODE AND FABRICATION METHOD OF A PHOTODIODE
    Publication number: 20230317744
    Abstract: A photodiode is formed in a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes a first N-type semiconductor region formed by epitaxial growth and a second N-type semiconductor region (that is more heavily doped than the first region) extending into the first N-type semiconductor region from the first surface. The dopant concentration of the first N-type semiconductor region gradually increases between the second surface and the first surface of the semiconductor substrate. An implanted heavily P-type doped region is formed in the second N-type semiconductor region at the first surface.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 5, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Boris RODRIGUES GONCALVES, Pascal FONTENEAU
  • Device comprising a transistor
    Patent number: 11776995
    Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: October 3, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
  • ELECTRONIC CHIP WITH TWO PHASE CHANGE MEMORIES
    Publication number: 20230309423
    Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.
    Type: Application
    Filed: May 22, 2023
    Publication date: September 28, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Remy BERTHELON, Franck ARNAUD
  • ELECTRONIC DEVICE
    Publication number: 20230299009
    Abstract: An electronic device includes a first electronic chip, a second electronic chip, and an interconnection circuit. A first region of a first surface of the first electronic chip is assembled by hybrid bonding to a third region of a third surface of the interconnection circuit. A second region of a second surface of the second electronic chip is assembled by hybrid to a fourth region of the third surface of the interconnection circuit. In this configuration, the first electronic chip is electrically coupled to the second electronic chip through the interconnection circuit. The first surface of the first electronic chip further includes a fifth region which is not in contact with the interconnection circuit. This fifth region includes a connection pad electrically connected by a connection element to a connection substrate to which the interconnection circuit is mounted.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 21, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Fady ABOUZEID, Philippe ROCHE
  • Image sensor with pixel matrix and microlens matrix having differing pitches from each other
    Patent number: 11764242
    Abstract: The present disclosure relates to an image sensor including a plurality of pixels formed in and on a semiconductor substrate and arranged in a matrix with N rows and M columns, with N being an integer greater than or equal to 1 and M an integer greater than or equal to 2. A plurality of microlenses face the substrate, and each of the microlenses is associated with a respective pixel. The microlenses are arranged in a matrix in N rows and M columns, and the pitch of the microlens matrix is greater than the pitch of the pixel matrix in a direction of the rows of the pixel matrix.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: September 19, 2023
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Lucie Dilhan, Jerome Vaillant
  • IMAGE SENSOR INTENDED TO BE ILLUMINATED VIA A BACK SIDE, AND CORRESPONDING METHOD FOR ACQUIRING A LIGHT FLUX
    Publication number: 20230290801
    Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY
  • CAPACITOR INCLUDING LATERAL PLATES AND METHOD FOR FORMING A CAPACITOR
    Publication number: 20230290813
    Abstract: A device includes at least one capacitor. The capacitor includes an assembly of two metal pads and at least two metal plates, each plate extending at least from one pad to the other, a first insulating layer conformally covering said assembly, a second conductive layer conformally covering the first layer.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 14, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Marios BARLAS
  • ELECTRONIC DEVICE
    Publication number: 20230290570
    Abstract: A device includes a first layer, having a copper track located therein. The first layer is covered with a second layer including a cavity. The cavity exposes at least a portion of the track. The portion is covered with a third layer of titanium nitride doped with silicon.
    Type: Application
    Filed: February 28, 2023
    Publication date: September 14, 2023
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Marios BARLAS, Yannick LE FRIEC, Xavier FEDERSPIEL
  • MOS TRANSISTOR ON SOI STRUCTURE
    Publication number: 20230290786
    Abstract: A device includes an active semiconductor layer on top of and in contact with an insulating layer which overlies a semiconductor substrate. A transistor for the device includes a source region, a drain region, and a body region arranged in the active semiconductor layer. The body region of the transistor is electrically coupled to the semiconductor substrate using a conductive via that crosses through the insulating layer.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 14, 2023
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Sebastien CREMER, Frederic MONSIEUR, Alain FLEURY, Sebastien HAENDLER
  • Optical diffuser and its method of manufacture
    Patent number: 11754758
    Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: September 12, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Vincent Farys, Alain Inard, Olivier Noblanc
  • Integrated optical sensor with pinned photodiodes
    Patent number: 11757054
    Abstract: An integrated optical sensor is formed by a pinned photodiode. A semiconductor substrate includes a first semiconductor region having a first type of conductivity located between a second semiconductor region having a second type of conductivity opposite to the first type one and a third semiconductor region having the second type of conductivity. The third semiconductor region is thicker, less doped and located deeper in the substrate than the second semiconductor region. The third semiconductor region includes both silicon and germanium. In one implementation, the germanium within the third semiconductor region has at least one concentration gradient. In another implementation, the germanium concentration within the third semiconductor region is substantially constant.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: September 12, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Didier Dutartre
  • Pixel and method for controlling the same
    Patent number: 11736826
    Abstract: A pixel includes: a detection node; a first normally on transistor connected between the detection node and a rail for applying a first potential; and a second transistor whose gate is connected to the detection node. An image sensor includes a plurality of the pixels and a control circuit configured to apply, during for a phase of initializing the detection node, the first potential to the gate of the first transistor.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: August 22, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Thomas Dalleau
  • X-ray detector
    Patent number: 11730433
    Abstract: An X-ray detector includes a first circuit with an NPN-type bipolar transistor and a second circuit configured to compare a voltage at a terminal of the NPN-type bipolar transistor with a reference value substantially equal to a value of the terminal voltage which would occur when the first circuit has been exposed to a threshold quantity of X-rays.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: August 22, 2023
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Gilles Gasiot, Severin Trochut, Olivier Le Neel, Victor Malherbe
  • CHIP CONTAINING AN ONBOARD NON-VOLATILE MEMORY COMPRISING A PHASE-CHANGE MATERIAL
    Publication number: 20230263082
    Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
    Type: Application
    Filed: April 3, 2023
    Publication date: August 17, 2023
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Franck ARNAUD, David GALPIN, Stephane ZOLL, Olivier HINSINGER, Laurent FAVENNEC, Jean-Pierre ODDOU, Lucile BROUSSOUS, Philippe BOIVIN, Olivier WEBER, Philippe BRUN, Pierre MORIN