Patents Assigned to STMicroelectronics (Crolles 2)
  • Patent number: 11025357
    Abstract: Systems, methods and devices are provided to improve management and accuracy of timestamps associated with sensor-based data. An indication is received of a sensor event associated with data samples provided from a sensor having an output data rate. A respective timestamp is assigned to each of the data samples. Assigning the respective timestamp may include, responsive to a determination that the indicated event is an interrupt event, calculating an actual data sampling interval based at least in part on time intervals between previous sensor events and a on a quantity of the one or more data samples.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics, Inc.
    Inventors: Karimuddin Sayed, Ashish Bhargava, Chandandeep Singh Pabla, Mahesh Chowdhary
  • Patent number: 11025289
    Abstract: A method for power management in an electronic circuit that comprises a processing system and an RF embedded circuit includes: generating a first regulated voltage with a power regulation module of the RF embedded circuit; generating a second regulated voltage from the first regulated voltage with a first linear regulator of the processing system; and controlling the power regulation module of the RF embedded circuit to operate according to a plurality of operation modes. The operation modes include: a first sleep mode in which a switched-mode power supply of the RF embedded circuit is off and a second linear regulator of the RF embedded circuit is off; a second sleep mode in which a switched-mode power supply is off and the second linear regulator is on; and a third sleep mode in which the switched-mode power supply is on and the second linear regulator is off.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Pasquale Butta′
  • Patent number: 11025263
    Abstract: An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Ramji Gupta
  • Patent number: 11025219
    Abstract: A filtering circuit includes at least two common-mode filters that are electrically coupled in series and magnetically coupled. The first common-mode filter includes first and second spiral inductors that are positively magnetically coupled and electrically isolated from each other. The second common-mode filter includes third and fourth spiral inductors that are positively magnetically coupled and electrically isolated from each other. The first and third spiral inductors are electrically connected in series and negatively magnetically coupled. Likewise, the second and fourth spiral inductors are electrically connected in series and negatively magnetically coupled.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Joel Concord
  • Patent number: 11023392
    Abstract: Access to a memory shared between a first interface and a second interface is arbitrated. Following a request to access the memory emanating from the second interface, while current access to the memory is granted to the first interface, a count is triggered having a maximum count time. A access to the memory is authorized for the second interface at the end of occupation of the access granted to the first interface if the end of occupation finishes before the end of the maximum count time, or otherwise at the end of the maximum count time.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jean-Louis Labyre
  • Publication number: 20210159308
    Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.
    Type: Application
    Filed: February 2, 2021
    Publication date: May 27, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • Publication number: 20210160672
    Abstract: A first object and a second object are movable in relation to one another. The first object includes a transponder using an integrated circuit having two terminals which may or may not be shorted. The presence or absence of a short circuit between the two terminals is detected. This is accomplished at least partly by the second object depending on the relative positioning of the first and second objects. The transponder transmits, to a module having a contactless reader function, positioning information corresponding to said relative positioning using a contactless communication protocol.
    Type: Application
    Filed: November 16, 2020
    Publication date: May 27, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Jean-Louis DEMESSINE
  • Publication number: 20210159785
    Abstract: A charge pump generates an output voltage. A first circuit generates a pulse width-modulated signal as a function of a deviation between the output voltage and a setpoint voltage. A second circuit receives a periodic signal and conditions the supply of the periodic signal to a control input of the charge pump as a function of the state of the pulse width-modulated signal.
    Type: Application
    Filed: November 16, 2020
    Publication date: May 27, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Xavier BRANCA
  • Patent number: 11016519
    Abstract: A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankit Gupta, Nitin Gupta, Prashutosh Gupta
  • Patent number: 11018576
    Abstract: A USB source device, supporting USB Power Delivery mode and coupled to a USB receiver device, includes a power converter delivering a supply voltage and a capacitive network coupled to the power converter. A method for managing the supply voltage on an output power supply pin of the USB source device includes discharging the capacitive network so as to reduce the supply voltage in response to a request to reduce the supply voltage by the USB receiver device to a target voltage. The method also includes delivering, to the power converter, a setpoint voltage for the supply voltage, a value of the setpoint voltage being reduced non-linearly so as to keep a temporal variation of the setpoint voltage lower than that of the supply voltage.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Christophe Lorin
  • Patent number: 11015218
    Abstract: A method for carrying out nucleic acid amplification, includes providing a reaction chamber, accommodating an array of nucleic acid probes at respective locations, for hybridizing to respective target nucleic acids; and introducing a solution into the reaction chamber, wherein the solution contains primers, capable of binding to target nucleic acids, nucleotides, nucleic acid extending enzymes and a sample including nucleic acids. The a structure of the nucleic acid probes and of the primers so that a hybridization temperature of the probes is higher than an annealing temperature of the primers, whereby hybridization and annealing take place in respective separate temperature ranges.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics S.R.L.
    Inventors: Enrico Alessi, Daniele Ricceri
  • Patent number: 11018601
    Abstract: A half-bridge driver circuit includes an amplifier configured to generate a measurement signal indicative of a current flowing through a shunt resistor. A processing circuit is configured to selectively acquire a sample of the measurement signal in response to a trigger signal. A synchronization circuit is configured to determine a first value indicative of the switch-on duration of a high side control signal, determine a second value indicative of the switching period of the high side control signal, compute a third value based on the first and second values, generate a third signal based on the third value when the next switching period of the high side control signal starts, start a second counter in response to the third signal, compare the count value of the second counter with a reference value to generate a fourth signal, and generate the trigger signal as a function of the fourth signal.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giuseppe D'Angelo
  • Patent number: 11018644
    Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics (Shenzen) R&D Co. Ltd.
    Inventors: XiangSheng Li, Ru Feng Du
  • Patent number: 11015933
    Abstract: A micromechanical detection structure includes a substrate of semiconductor material and a driving-mass arrangement is coupled to a set of driving electrodes and driven in a driving movement following upon biasing of the set of driving electrodes. A first anchorage unit is coupled to the driving-mass arrangement for elastically coupling the driving-mass arrangement to the substrate at first anchorages. A driven-mass arrangement is elastically coupled to the driving-mass arrangement by a coupling unit and designed to be driven by the driving movement. A second anchorage unit is coupled to the driven-mass arrangement for elastically coupling the driven-mass arrangement to the substrate at second anchorages. Following upon the driving movement, the resultant of the forces and of the torques exerted on the substrate at the first and second anchorages is substantially zero.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Gattere, Luca Giuseppe Falorni, Carlo Valzasina
  • Patent number: 11018640
    Abstract: A differential amplifier includes: first and second input nodes; first and second output nodes; first and second supply nodes; first and second offset compensation nodes; first and second amplifier staged configured to generate first and second output voltages at the first and second output nodes as a function of first and second input voltages of the first and second input nodes and first and second offset compensation voltages of the first and second offset compensation nodes; and a feedback circuit configured to generate the first and second offset compensation voltages as a function of the first and the second output voltages. The feedback circuit includes: a coupling circuit coupled between the first and second offset compensation nodes, wherein the coupling circuit comprises one or more passive electric components.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventor: Daniele Grasso
  • Patent number: 11018096
    Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: May 25, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Eric Sabouret, Krysten Rochereau, Olivier Hinsinger, Flore Persin-Crelerot
  • Publication number: 20210151600
    Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 20, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean JIMENEZ MARTINEZ
  • Publication number: 20210151559
    Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 20, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean JIMENEZ MARTINEZ
  • Publication number: 20210151392
    Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.
    Type: Application
    Filed: January 27, 2021
    Publication date: May 20, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak MARZAKI, Pascal FORNARA
  • Publication number: 20210151616
    Abstract: An integrated optical sensor includes a photon-detection module of a single-photon avalanche photodiode type. The detection module includes a semiconductive active zone in a substrate. The semiconductive active zone includes a region that contains germanium with a percentage between 3% and 10%. This percentage range is advantageous because it makes it possible to obtain a material firstly containing germanium (which in particular increases the efficiency of the sensor in the infrared or near infrared domain) and secondly having no or very few dislocations(which facilitates the implementation of a functional sensor in integrated form).
    Type: Application
    Filed: November 13, 2020
    Publication date: May 20, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Didier DUTARTRE