Patents Assigned to STMicroelectronics (Crolles 2)
  • METHOD FOR DEPOSITING A SILICON OXIDE LAYER OF SAME THICKNESS ON SILICON AND ON SILICON-GERMANIUM
    Publication number: 20130072032
    Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.
    Type: Application
    Filed: July 27, 2012
    Publication date: March 21, 2013
    Applicants: STMicroelectronics S.A., International Business Machines Corporation, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Nicolas Breil, Yves Campidelli, Olivier Gourhant
  • METHOD FOR FORMING A SILICIDE LAYER AT THE BOTTOM OF A HOLE AND DEVICE FOR IMPLEMENTING SAID METHOD
    Publication number: 20130065392
    Abstract: A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 14, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Magali Gregoire
  • SRAM DIMENSIONED TO PROVIDE BETA RATIO SUPPORTING READ STABILITY AND REDUCED WRITE TIME
    Publication number: 20130058155
    Abstract: A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup transistor and a pulldown transistor. A product formed by a ratio of the pulldown transistor gate width to the access transistor gate width multiplied by a ratio of the access transistor gate length to the pulldown transistor gate length is smaller than one. Furthermore, the pullup transistor gate width is greater than or equal to the pulldown transistor gate width.
    Type: Application
    Filed: August 24, 2012
    Publication date: March 7, 2013
    Applicants: STMICROELECTRONICS PVT LTD, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Olivier Callen, Anuj Grover, Tanmoy Roy
  • PHOTOLITHOGRAPHY METHOD USING A CHEMICALLY-AMPLIFIED RESIST
    Publication number: 20130059254
    Abstract: A photolithography method, including the steps of: S1) depositing, on the upper surface of a wafer, a chemically-amplified resist; S2) exposing the resist to a sensitizing radiation through a mask, to generate acid compounds in the exposed regions; S3) heating the resist, to have the acid compounds react with dissolution-inhibiting groups; and S5) developing the resist; and including, after step S3, a step of neutralization, S4, of the acid compounds which have not reacted at step S3.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 7, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Benedicte Mortini
  • METHOD FOR FORMING AN ISOLATION TRENCH
    Publication number: 20130056845
    Abstract: A method forms at least one isolation trench in a substrate having an upper surface. The method includes at least: forming, across the substrate thickness, at least one first cavity opened towards the upper surface; totally filling this first cavity with a dielectric material of a first type; forming a second cavity in an upper portion of the first cavity thus filled, said second cavity being opened towards the upper surface and having a substantially concave profile; totally filling this second cavity with a dielectric material of a second type; and leveling the free surface of the trench substantially down to the upper surface level.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 7, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Laurent Favennec, Cedric Perrot
  • PHOTOSITE WITH PINNED PHOTODIODE
    Publication number: 20130049155
    Abstract: A photosite is formed in a semiconductor substrate and includes a photodiode confined in a direction orthogonal to the surface of the substrate. The photodiode includes a semiconductor zone for storing charge that is formed in an upper semiconductor region having a first conductivity type and includes a main well of a second conductivity type opposite the first conductivity type and laterally pinned in a first direction parallel to the surface of the substrate. The photodiode further includes an additional semiconductor zone including an additional well having the second conductivity type that is buried under and makes contact with the main well.
    Type: Application
    Filed: June 21, 2012
    Publication date: February 28, 2013
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS S.A.
    Inventors: Francois Roy, Julien Michelot
  • METHOD FOR PRODUCING A DEEP TRENCH IN A MICROELECTRONIC COMPONENT SUBSTRATE
    Publication number: 20130052829
    Abstract: A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.
    Type: Application
    Filed: August 30, 2012
    Publication date: February 28, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Leverd, Laurent Favennec, Arnaud Tournier
  • METHOD OF DETERMINING FOCUS AND DOSE OF AN APPARATUS OF OPTICAL MICRO-LITHOGRAPHY
    Publication number: 20130040230
    Abstract: In one or more embodiments, the disclosure relates to a method of setting a photolithography exposure machine, comprising: forming on a photolithography mask test patterns and circuit patterns, transferring the patterns to a resin layer covering a wafer, measuring a critical dimension of each test pattern transferred, and determining a focus setting error value of the photolithography machine from the measure of the critical dimension of each pattern, the test patterns formed on the mask comprising a first reference test pattern and a second test pattern forming for a photon beam emitted by the photolithography machine and going through the mask, an optical path having a length different from an optical path formed by the first test pattern and the circuit patterns formed on the mask.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 14, 2013
    Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Nicolas Spaziani, Jean Massin
  • INTEGRATED DRAM MEMORY DEVICE
    Publication number: 20130039113
    Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.
    Type: Application
    Filed: January 20, 2011
    Publication date: February 14, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sébastien Cremer, Frédérìc Lalanne, Marc Vernet
  • Compact field effect transistor with counter-electrode and fabrication method
    Patent number: 8368128
    Abstract: An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on insulator type. The substrate is covered by a layer of dielectric material and a gate material. The counter-electrode contact is located in the pattern of the gate electrode. The gate material is etched to define the gate electrode, the source contact and drain contacts and the counter-electrode contact. A part of the support substrate is released through the pattern of the counter-electrode contact area. An electrically conductive material is deposited on the free part of the support substrate to form the counter-electrode contact.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 5, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Claire Fenouillet-Béranger, Olivier Thomas, Philippe Coronel, Stéphane Denorme
  • Image capture unit
    Patent number: 8367454
    Abstract: An image capture unit and its manufacturing method. The image capture unit includes a thinned-down integrated circuit chip having an image sensor on its upper surface side. A wall extends above a peripheral upper surface ring-shaped area, and a lens rests on the high portion of the wall.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: February 5, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Xavier Gagnard
  • INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD
    Publication number: 20130026546
    Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench including an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer including nitrogen or carbon.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 31, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Favennec, Arnaud Tournier, François Roy
  • TRANSFORMER OF THE BALANCED-UNBALANCED TYPE
    Publication number: 20130026846
    Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 31, 2013
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic Gianesello, Romain Pilard, Cedric Durand
  • ELECTRONIC CHIP COMPRISING CONNECTION PILLARS AND MANUFACTURING METHOD
    Publication number: 20130026627
    Abstract: An electronic chip including a semiconductor substrate (1) covered with an insulating layer (4) including metal interconnection levels (3) and interconnection pillars (10) connected to said metal interconnection levels (3), said pillars (110) forming regions (111) protruding from the upper surface of said insulating layer (4) and capable of forming an electric contact, wherein said pillars (110) have a built-in portion (115) in a housing formed across the thickness of at least said insulating layer (4).
    Type: Application
    Filed: July 20, 2012
    Publication date: January 31, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • INTEGRATED MILLIMETER WAVE TRANSCEIVER
    Publication number: 20130027274
    Abstract: A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on an electronic device; at least one integrated circuit chip assembled on the upper surface of the interposer; at least one antenna including at least one track formed on the upper surface of the interposer; and at least one block attached under the plate and including in front of each antenna a cavity having a metalized bottom, the distance between each antenna and the bottom being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.
    Type: Application
    Filed: June 6, 2012
    Publication date: January 31, 2013
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-François Carpentier, Laurent Dussopt, Henri Sibuet
  • MIM transistor
    Patent number: 8354725
    Abstract: The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: January 15, 2013
    Assignee: STMicroelectronics Crolles 2 SAS
    Inventors: Benoit Froment, Etienne Robilliart
  • Electric via comprising lateral outgrowths
    Patent number: 8350363
    Abstract: A via connecting the front surface of a substrate to its rear surface, this substrate including a porous region extending from at least a portion of the periphery of the via, the via including outgrowths extending in pores of the porous region.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: January 8, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Hamed Chaabouni, Lionel Cadix
  • PARTIAL WRITE ON A LOW POWER MEMORY ARCHITECTURE
    Publication number: 20130003484
    Abstract: A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 3, 2013
    Applicants: STMicroelectronics (CROLLES 2) SAS, STMicroelectronics Pvt Ltd.
    Inventors: Anuj PARASHAR, Marc Vernet
  • INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD
    Publication number: 20120319206
    Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 20, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
  • ELECTRONIC COMPONENT COMPRISING A NUMBER OF MOSFET TRANSISTORS AND MANUFACTURING METHOD
    Publication number: 20120313182
    Abstract: An electronic component including a number of insulated-gate field effect transistors, said transistors belonging to at least two distinct subsets by virtue of their threshold voltage, wherein each transistor includes a gate that has two electrodes, namely a first electrode embedded inside the substrate where the channel of the transistor is defined and a second upper electrode located above the substrate facing buried electrode relative to channel and separated from said channel by a layer of dielectric material and wherein the embedded electrodes of all the transistors are formed by an identical material, the upper electrodes having a layer that is in contact with the dielectric material which is formed by materials that differ from one subset of transistors to another.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 13, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean Luc Huguenin, Stéphane Monfray