Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
Type:
Grant
Filed:
May 22, 2023
Date of Patent:
April 16, 2024
Assignees:
STMicroelectronics (Alps) SAS, STMicroelectronics (Grand Ouest) SAS
Abstract: In at least one embodiment, a Geiger-mode avalanche photodiode, including a semiconductor body, is provided. The semiconductor body includes a semiconductive structure and a front epitaxial layer on the semiconductive structure. The front epitaxial layer has a first conductivity type. An anode region having a second conductivity type that is different from the first conductivity type extends into the front epitaxial layer. The photodiode further includes a plurality of gettering regions in the semiconductive structure.
Abstract: In some embodiments, a ToF sensor includes an illumination source module, a transmitter lens module, a receiver lens module, and an integrated circuit that includes a ToF imaging array. The ToF imaging array includes a plurality of SPADs and a plurality of ToF channels coupled to the plurality of SPADs. In a first mode, the ToF imaging array is configured to select a first group of SPADs corresponding to a first FoV. In a second mode, the ToF imaging array is configured to select a second group of SPADs corresponding to a second FoV different than the first FoV.
Abstract: Described herein is a time-of-flight ranging system and methods for its operation. The system includes an array of single photon avalanche diode (SPAD) pixels and control circuitry. The control circuitry simultaneously accumulates integrated SPAD event data from one cluster of SPAD pixels while integrating SPAD event data from another cluster during different target illuminations. The system also includes first and second VCSEL clusters, each responsible for a different target illumination. By processing and managing the data in this manner, the system can effectively reduce the time used to gather and analyze the event data, leading to faster and more accurate distance measurements.
Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.
Abstract: In a DC-DC converter, a duty-cycle control signal is generated in response to comparing the switching stage output voltage and a reference voltage signal. A first circuit compares the duty-cycle control signal and a ramp to produce a PWM signal. A second circuit compares the duty-cycle control signal and a skip threshold to produce a skip control signal which halts switching operation of the switching stage. A count is made of number of periods of the skip control signal during a monitoring time window and the number of periods of a clock signal during a period of the skip control signal is counted. When the counted number of skip control signal periods is within a first range and the counted number of clock signal periods is within a second range, a common detection signal is asserted to trigger varying a value of the skip threshold signal.
Type:
Application
Filed:
October 3, 2023
Publication date:
April 11, 2024
Applicant:
STMicroelectronics S.r.l.
Inventors:
Alessandro BERTOLINI, Alberto CATTANI, Alessandro GASPARINI
Abstract: System, method, and circuitry for generating a linker model for use by a toolchain associated with a programmable computing device. One or more regions in the memory resources available to the programmable computing devices is defined for used by an application executing on the programmable computing device. One or more sections is defined for those regions for use by the application. Resource boundaries are generated for the application based on the defined regions and the defined sections. A user is enabled to modify the defined regions or the defined sections or the generated resource boundaries. A linker model is then generated based on the available memory resources, the defined regions, the defined sections, and the generated resource boundaries. This linker model is then utilized to generate a linker script for the programmable computing device based the linker syntax compatible with a toolchain linker for the programmable computing device.
Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.
Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.
Type:
Application
Filed:
December 20, 2023
Publication date:
April 11, 2024
Applicants:
STMicroelectronics S.r.l., STMicroelectronics SDN BHD
Inventors:
Andrea ALBERTINETTI, Marifi Corregidor CAGUD
Abstract: According to one aspect, an integrated circuit includes: an electronic module configured to generate a voltage at an output, and an electronic control circuit coupled to an output of the electronic module, the electronic control circuit comprising an emissive electronic component. The electronic control circuit is configured to cause the emissive electronic component to emit light radiation as a function of a value of the voltage at the output of the electronic module relative to a value of an operating voltage of the electronic module, and the operating voltage is specific thereto during normal operation of this electronic module. The light radiation emitted by the emissive electronic component is configured to diffuse to an outer face of the integrated circuit.
Type:
Grant
Filed:
March 9, 2023
Date of Patent:
April 9, 2024
Assignees:
STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
Inventors:
Etienne Auvray, Tommaso Melis, Philippe Sirito-Olivier
Abstract: An embodiment method comprises collecting at least one electrophysiological signal of a human over a limited time duration, and computing a set of electrophysiological signal features. The computing comprises at least one of: providing at least one reference electrophysiological signal and applying dynamic time warping processing to the at least one collected and at least one reference electrophysiological signals, applying stacked-auto-encoder artificial neural network processing to the collected electrophysiological signal, or filtering the electrophysiological signal collected via joint low-pass and high-pass filtering. The method further comprises applying pattern recognition processing to the computed set of features, producing a virtual key signal indicative of an identity of the human, and applying the virtual key signal to a user circuit to switch it between a first state and a second state as a result of the virtual key signal matching an authorized key signal stored in the user circuit.
Type:
Grant
Filed:
September 1, 2020
Date of Patent:
April 9, 2024
Assignee:
STMicroelectronics S.r.l.
Inventors:
Francesco Rundo, Sabrina Conoci, Concetto Spampinato
Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.
Type:
Grant
Filed:
November 5, 2021
Date of Patent:
April 9, 2024
Assignees:
STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Rousset) SAS
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
Type:
Grant
Filed:
May 24, 2021
Date of Patent:
April 9, 2024
Assignees:
STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
Abstract: A time series of face images of a human during a human activity are captured. A first artificial neural network (ANN) processing pipeline processes the captured time series of face images to provide a first attention level indicator signal. An electrophysiological signal indicative of the level of attention of the human during the activity is also captured. A second ANN processing pipeline processes the sensed electrophysiological signal to providing a second attention level indicator signal. A risk indicator signal is then generated based on at least one of the first attention level indicator and second attention level indicator. A user circuit is then triggered as a result of the risk indicator reaching or failing to reach at least one attention level threshold.
Type:
Grant
Filed:
April 7, 2022
Date of Patent:
April 9, 2024
Assignee:
STMicroelectronics S.r.l.
Inventors:
Francesco Rundo, Giancarlo Asnaghi, Sabrina Conoci
Abstract: In an embodiment the method a includes performing, by an integrated circuit (IC) card hosted in a local equipment, authentication with a contactless subscriber device when the subscriber device is within a communication range of a contactless interface of the local equipment, receiving, by the IC card, an identifier (SID) identifying a software module from the subscriber device, the software module configured to enable a subscription profile for a mobile network operator, performing a checking operation at the IC card whether the SID matches a software module identifier stored in the IC card and selectively performing one of downloading the software module to the IC card, enabling the software module at the IC card or disabling the software module at the IC card as a result of performing the checking operation.
Abstract: An integrated circuit includes sensing circuitry and processing circuitry. The processing circuitry processes received sensor-session requests and received sensor-service requests. Processing a received sensor-service request includes determining a type of the received sensor-service request. In response to determining the received sensor-service request is of a first type, results information is generated in response to the received sensor-service request of the first type based on sensor data generated by the sensing circuitry. In response to determining the received sensor-service request is of a second type, remote-server processing based on the received sensor-service request of the second type is initiated, and a response to the received sensor-service request of the second type is generated based on a received response to the initiated remote-server processing.
Abstract: A method to operate a DC-DC power converter in a low power burst mode, the method including sampling an output voltage of the DC-DC power converter with a sampling frequency to determine when to initiate a burst for the low power burst mode; and adapting the sampling frequency based on the output voltage.
Type:
Grant
Filed:
July 28, 2021
Date of Patent:
April 9, 2024
Assignee:
STMicroelectronics S.r.l.
Inventors:
Alessandro Nicolosi, Giovanni Sicurella
Abstract: Disclosed herein is a microelectromechanical device that features a fixed structure defining a cavity, a tiltable structure elastically suspended within the cavity, and a piezoelectrically driven actuation structure that rotates the tiltable structure about a first rotation axis. The actuation structure includes driving arms with piezoelectric material, elastically coupled to the tiltable structure by decoupling elastic elements that are stiff to out-of-plane movements but compliant to torsional movements. The tiltable structure is elastically coupled to the fixed structure at the first rotation axis using elastic suspension elements, while the fixed structure forms a frame surrounding the cavity with supporting elements. A lever mechanism is coupled between a supporting element and a driving arm.
Abstract: A method of processing information of a rotating wheel includes measuring angular velocity of a rotating wheel with a gyroscopic sensor, determining an instantaneous position of the rotating wheel with an accelerometer, and determining the angular positions of the rotating wheel based on the measured angular velocity and the instantaneous position of the rotating wheel. The gyroscopic sensor and the accelerometer are mounted on the rotating wheel.
Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.