Abstract: A method of starting a permanent magnet synchronous motor (PMSM) with field oriented control (FOC) includes: opening a first control loop of the PMSM; setting a first direction for a first current component of the PMSM; aligning a rotor of the PMSM to the first direction; after aligning the rotor, setting a second direction for the first current component, where the second direction is rotated from the first direction by 90 degrees; after setting the second direction, starting the rotor while the first control loop of the PMSM remains open; after starting the rotor, increasing a rotation speed of the rotor by operating the first control loop in a first closed-loop mode; and after increasing the rotation speed of the rotor, controlling the rotation speed of the rotor by operating the first control loop in a second closed-loop mode different from the first closed-loop mode.

Abstract: A method for operating a wireless charging transmitter includes switching, by the wireless charging transmitter, an operating mode of a full bridge inverter of the wireless charging transmitter from a first mode to a second mode; and changing, by the wireless charging transmitter, an operating point of the wireless charging transmitter from a first operating point associated with the first mode to a second operating point associated with the second mode, the second operating point being selected to dampen a change in a rectifier voltage of a wireless charging receiver inductively coupled to the wireless charging transmitter.

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

Abstract: In accordance with an embodiment, a hard disk drive includes voice coil motors (VCMs) coupled to respective control units configured to drive retract an operation of the VCMs in the hard disk drive. The retract operation of the VCMs includes a sequence of retract steps. The control units are allotted respective time slots for communication over a communication line with the respective time slots synchronized via the common clock line, and are configured to drive sequences of retract steps of the VCMs in the hard disk drive in a timed relationship.

Abstract: The present disclosure is directed to a device and method for detecting presence or absence of human speech. The device and method utilize a low-power accelerometer. The device and method generate an acceleration signal using the accelerometer, filter the acceleration signal with a band pass filter or a high pass filter, determine at least one calculation of the filtered acceleration signal, detect a presence or absence of a voice based on the at least one calculation, and output a detection signal that indicates the presence or absence of the voice. The device and method are well suited for portable audio devices, such as true wireless stereo headphones, that have a limited power supply.

Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.

Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.

Abstract: In accordance with an embodiment, a detection device includes: an infrared temperature sensor configured to provide a temperature signal associated with an heat emission of at least one individual within a monitored area; an electrostatic-charge-variation sensor configured to provide a charge-variation signal indicative of a variation of electrostatic charge associated with the at least one individual; and a processing unit, coupled to the infrared temperature sensor and to the electrostatic-charge-variation sensor, the processing unit configured to detect a presence of the at least one individual within the monitored area by receiving the temperature signal and the charge-variation signal, and jointly processing the temperature signal and charge.

Abstract: A digital image sensor package includes an image sensor substrate and a glass covering. The image sensor substrate carries photodiodes. The glass covering has a bottom surface, a top surface opposite the bottom surface, and a sidewall delimiting a perimeter edge of the glass covering. The glass covering overlies the photodiodes. A surface area of the top surface of the glass covering is greater than a surface area of the bottom surface of the glass covering such that the sidewall is anti-perpendicular to the top and bottom surfaces of the glass.

Abstract: In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.

Abstract: The present description concerns an electronic device comprising: a silicon layer, an insulating layer in contact with a first surface of the silicon layer, a transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the device further comprising, under the gate portion, a partial insulating trench in the silicon layer extending from a second surface of the silicon layer down to a depth smaller than the thickness of the silicon layer.

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

Abstract: The present disclosure is directed to a wearable electronic device, such as a watch, that includes one or more optical sensors. In order to determine accuracy of measurements by the optical sensors, the device detects whether or not the optical sensors are in physical contact with the user's skin. The device detects a level of contact between the user's skin and the optical sensors based on electrostatic charge variation measurements, and generates a contact reliability index (CRI) based on the level of contact. Operation of the optical sensors are adjusted based on the CRI.

Abstract: A method of pairing between a first host device and a first peripheral device includes entering by a user of the first host device a verification value, as well as comparing, by the first peripheral device, between the verification value and a first secret value stored in a memory of the first peripheral device. When the verification corresponds to the first secret value, the method of pairing further includes calculating and storing a first pairing key by the first host device and the first peripheral device to perform the pairing.

Abstract: An integrated circuit includes a memory and processing circuitry. The memory stores an Elementary File Test (EFT) file including a record storing information to update a target elementary file (TGF) in a file system of the EFT. The stored information includes a file path identifier identifying a position of the TGF in the file system of the EFT file, which is a concatenation of a parent file identifier followed by an identifier of the TGF, a first length indicator of a first type of data, the data of the first type, a second length indicator to indicate a length of a second type of data, and the data of the second type. The processing circuitry, in operation, identifies the TGF based on the file path identifier and updates the content of the TGF to include the first data and one or more instances of the second data.

Abstract: The present description concerns an electronic device comprising: —a silicon layer having a first surface and a second surface, —an insulating layer in contact with the first surface of the silicon layer, —at least one transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the gate portion being less heavily doped than the rest of the gate region.

Abstract: An AC capacitor is coupled to a totem-pole type PFC circuit. In response to detection of a power input disconnection, the PFC circuit is controlled to discharge the AC capacitor. The PFC circuit includes a resistor and a first MOSFET and a second MOSFET coupled in series between DC output nodes with a common node coupled to the AC capacitor. When the disconnection event is detected, one of the first and second MOSFETs is turned on to discharge the AC capacitor with a current flowing through the resistor and the turned on MOSFET. Furthermore, a thyristor may be simultaneously turned on, with the discharge current flowing through a series coupling of the MOSFET, resistor and thyristor. Disconnection is detected by detecting a zero-crossing failure of an AC power input voltage or lack of input voltage decrease or input current increase in response to MOSFET turn on for a DC input.

Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.

Abstract: In accordance with an embodiment, a linear voltage regulator includes: a first transistor coupled between a first input terminal and an output terminal, the first input terminal adapted to receive a first voltage, and the output terminal adapted to provide a regulated voltage; a second transistor coupled between a second input terminal and the output terminal, the second input terminal adapted to receive a second voltage; and an amplifier of a difference between a third voltage proportional to the voltage at the output terminal and a reference voltage, an output of said amplifier being selectively coupled to a control terminal of the first transistor and to a control terminal of the second transistor, the amplifier being supplied by a fourth voltage corresponding to a highest voltage of the first voltage and the second voltage.