Patents Assigned to STMicroelectronics (Crolles 2)
  • Very small image sensor
    Patent number: 8193479
    Abstract: An image sensor formed in a semiconductor stack of a lower region of a first conductivity type and of an upper region of a second conductivity type, including: a photodiode formed of a first portion of the stack; a read area formed of a second portion of the stack; a trench with insulated walls filled with a conductive material, the trench surrounding the photodiode and the read area and being interrupted, all along its height, on a portion facing the photodiode and the read area; and first connection mechanism associated with the conductive material of the trench and capable of being connected to a reference bias voltage.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: June 5, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: François Roy, Benoît Ramadout
  • SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA, AND FABRICATION METHOD
    Publication number: 20120133021
    Abstract: A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 31, 2012
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS S.A.
    Inventors: Sylvain Joblot, Alexy Farcy, Jean-Francois Carpentier, Pierre Bar
  • Assembly of two parts of an integrated electronic circuit
    Patent number: 8186568
    Abstract: A process for assembling two parts of an integrated electronic circuit has two successive steps. During a first step, the two circuit parts are made into a single unit by molecular bonding, realized on respective application surfaces of the two parts. During a second step, electrical connections are formed from connection portions already present in the application surfaces of the two circuit parts. The connections formed extend across the bonding interface, and are compatible with a high reliability and a high level of integration of the circuit.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: May 29, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Coronel, Perceval Coudrain, Pascale Mazoyer
  • Device with integrated circuit and encapsulated N/MEMS and method for production
    Patent number: 8183078
    Abstract: A method for producing a device including at least one integrated circuit and at least one N/MEMS. The method produces the N/MEMS in at least one upper layer arranged at least above a first section of a substrate, produces the integrated circuit in a second section of the substrate and/or in a semiconductor layer arranged at least above the second section of the substrate, and further produces a cover encapsulating the N/MEMS from at least one layer used for production of a gate in the integrated circuit and/or for producing at least one electrical contact of the integrated circuit.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: May 22, 2012
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Eric Ollier, Thomas Baron
  • Electronic circuit output stage
    Patent number: 8183926
    Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: May 22, 2012
    Assignee: STMicroelectronics (Crolles2) SAS
    Inventor: Hubert Degoirat
  • Method for manufacturing a structure of semiconductor-on-insulator type
    Patent number: 8178426
    Abstract: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: May 15, 2012
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Yves Morand, Yves Campidelli, Olivier Kermarrec
  • INTEGRATED CIRCUIT WITH PROTECTION FROM COPPER EXTRUSION
    Publication number: 20120112259
    Abstract: An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The element may be electrically connected to and spaced away from a copper line of the metallization level by way of an electrical link passing through the barrier layer and including an electrically conductive material different from copper in direct contact with the copper line.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 10, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien CREMER, Sébastien Gaillard
  • METHOD FOR FORMING A MULTILAYER STRUCTURE
    Publication number: 20120115311
    Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 10, 2012
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien DESPLOBAIN, Frederic-Xavier GAILLARD, Yves MORAND, Fabrice NEMOUCHI
  • Transistor or triode structure with tunneling effect and insulating nanochannel
    Patent number: 8173992
    Abstract: A microelectronic device is provided with at least one transistor or triode with Fowler-Nordheim tunneling current modulation, and supported on a substrate. The triode or the transistor includes at least one first block forming a cathode and at least one second block forming an anode. The first block and the second block are supported on the substrate, and are separated from each other by a channel insulating zone also supported on the substrate. A gate dielectric zone is supported on at least the channel insulating zone, and a gate is supported on the gate dielectric zone.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: May 8, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Thomas Skotnicki, Stephane Monfray
  • High-stability thin-film capacitor and method for making the same
    Patent number: 8169771
    Abstract: The dielectric of a capacitor is formed by superposition of at least two thin layers made from the same metal oxide, respectively in crystalline and amorphous form and respectively presenting quadratic voltage coefficients of capacitance of opposite signs.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: May 1, 2012
    Assignees: Commissariat a l'Energie Atomique, STMicroelectronics (Crolles 2) S.A.S.
    Inventors: Emmanuel Defay, Julie Guillan, Serge Blonkowski
  • SIMPLIFIED COPPER-COPPER BONDING
    Publication number: 20120100657
    Abstract: A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.
    Type: Application
    Filed: July 1, 2010
    Publication date: April 26, 2012
    Applicants: Stmicroelectronics (Crolles 2) SAS, Commisariat A L'Energie Atomique et Aux Ene Alt
    Inventors: Lea Di Cioccio, Pierric Gueguen, Maurice Rivoire
  • METHOD FOR FORMING INTEGRATED CIRCUITS ON A STRAINED SEMICONDUCTOR SUBSTRATE
    Publication number: 20120094470
    Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
    Type: Application
    Filed: September 22, 2011
    Publication date: April 19, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Bensahel, Aomar Halimaoui
  • Microresonator
    Patent number: 8159109
    Abstract: A microresonator comprising a single-crystal silicon resonant element and at least one activation electrode placed close to the resonant element, in which the resonant element is placed in an opening of a semiconductor layer covering a substrate, the activation electrode being formed in the semiconductor layer and being level at the opening.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: April 17, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Nicolas Abelé, Pascal Ancey, Alexandre Talbot, Karim Segueni, Guillaume Bouche, Thomas Skotnicki, Stéphane Monfray, Fabrice Casset
  • Antenna Array for Transmission/Reception Device for Signals with a Wavelength of the Microwave, Millimeter or Terahertz Type
    Publication number: 20120086608
    Abstract: Transmission/reception device for signals having a wavelength of the microwaves, millimeter or terahertz type, comprising an antenna array. The antenna array comprises a first group of first omni-directional antennas and a second group of second directional antennas disposed around the first group of antennas.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 12, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Andreia Cathelin, Mathieu Egot, Romain Pilard, Daniel Gloria
  • READ BOOST CIRCUIT FOR MEMORY DEVICE
    Publication number: 20120081978
    Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.
    Type: Application
    Filed: September 22, 2011
    Publication date: April 5, 2012
    Applicants: STMicroelectronics S.A., Centre National de la Recherche Scientifique, STMicroelectronics Crolles 2 SAS
    Inventors: Fady Abouzeid, Sylvain Clerc, Philippe Roche
  • METHOD FOR MANUFACTURING MOS TRANSISTORS WITH DIFFERENT TYPES OF GATE STACKS
    Publication number: 20120083110
    Abstract: A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing.
    Type: Application
    Filed: September 20, 2011
    Publication date: April 5, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Luc Huguenin, Grégory Bidal
  • INTEGRATED CIRCUIT COMPRISING A DEVICE WITH A VERTICAL MOBILE ELEMENT INTEGRATED IN A SUPPORT SUBSTRATE AND METHOD FOR PRODUCING THE DEVICE WITH A MOBILE ELEMENT
    Publication number: 20120074527
    Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 29, 2012
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Fabrice Casset, Lionel Cadix, Perceval Coudrain, Alexis Farcy, Laúrent-Lüc Chapelon, Yacine Felk, Pascal Ancey
  • Method for forming metal interconnects in a dielectric material
    Patent number: 8138082
    Abstract: A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: March 20, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninkljike Philips Electronics N.V.
    Inventors: Joaquin Torres, Vincent Arnal, Laurent-Georges Gosset, Wim Besling
  • METHOD AND DEVICE FOR MEASURING THE RELIABILITY OF AN INTEGRATED CIRCUIT
    Publication number: 20120062268
    Abstract: Electromigration may cause a fault to appear in an integrated circuit located on a semiconductor chip. To detect such a fault, at least one resistive test structure is provided separated from the integrated circuit and located on at least one metallization level of the integrated circuit. During operation of the integrated circuit, the resistive test structure is sensed. Detection of a voltage difference between two points of the resistive test structure is indicative of a fault.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 15, 2012
    Applicants: STMICROELECTRONICS PVT LTD., STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Remy Chevallier, Vincent Huard, Neeraj Kapoor, Xavier Federspiel
  • SINGLE-PORT MEMORY ACCESS CONTROL DEVICE
    Publication number: 20120054464
    Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocs of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.
    Type: Application
    Filed: August 30, 2011
    Publication date: March 1, 2012
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Cédric Minne