Abstract: In accordance with an embodiment, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes: measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source; measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source; measure a third voltage across the current sensing resistor; and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage and the measured third voltage.

Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a first doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.

Abstract: A method implemented by a wireless charging receiver (RX) includes detecting, by the wireless charging RX, that a voltage potential of an output of a rectifier of the wireless charging RX has met a boost mode threshold; placing, by the wireless charging RX, the rectifier into a boost mode; and detecting, by the wireless charging RX, that the voltage potential of the output of the rectifier of the wireless charging RX has met a specified threshold, and based thereon, negotiating, by the wireless charging RX with a wireless charging transmitter (TX), to initiate a power transfer.

Abstract: The present disclosure relates to a method including the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.

Abstract: In certain embodiments, a method includes accessing image information for a scene in a movement path of a mobile robot. The image includes image information for each of a plurality of pixels of the scene, the image information comprising respective intensity values and respective distance values. The method includes analyzing the image information to determine whether to modify the movement path of the mobile robot. The method includes initiating, in response to determining according to the image information to modify the movement path of the mobile robot, sending of a command to a drive subsystem of the mobile robot to modify the movement path of the mobile robot.

Abstract: An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.

Abstract: In an example, a display device includes a rollable display including a display side and an opposite non-display side. The rollable display includes a conductive material with a pattern disposed on the non-display side. The device includes a housing configured to house the rollable display and configured to roll in and roll out the rollable display along a first direction, and a capacitive sensor including a transmitter and a receiver electrode disposed within the housing and configured to sense the pattern.

Abstract: A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.

Abstract: The vertical-conduction electronic power device is formed by a body of wide band gap semiconductor which has a first conductivity type and has a surface, and is formed by a drift region and by a plurality of surface portions delimited by the surface. The electronic device is further formed by a plurality of first implanted regions having a second conductivity type, which extend into the drift region from the surface, and by a plurality of metal portions, which are arranged on the surface. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a plurality of Schottky diodes formed by first Schottky diodes and second Schottky diodes, wherein the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from that of the second Schottky diodes.

Abstract: A wireless power-reception system has a bridge rectifier with two high-side and two low-side transistors, linked to input-nodes and sense-resistors. During a first phase, a control circuit activates certain transistors for rectification, producing an output voltage, while modulating a gate voltage of a non-activated low-side transistor to dissipate excess power and regulate the output voltage. During a first given number of occurrences of the first phase, the control circuit determines the current through the low-side transistor having its gate voltage modulated based upon a voltage across a first sense resistor coupled between that low-side transistor and ground. During a second given number of occurrences of the first phase, the control circuit determines the current delivered to the load based upon a voltage across the first sense resistor and a voltage across a second sense resistor coupled between the other low-side transistor and ground.

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

Abstract: A measurement system, featuring first and second capacitances, and switching, control, and measurement circuits, charges/discharges the capacitances during normal operation. The switching and control circuits periodically connect a first terminal of the first capacitance to a first voltage and a reference voltage, and a first terminal of the second capacitance to a second voltage and the reference voltage. The second terminal of the first capacitance and the second terminal of the second capacitance are connected to the input terminals of the differential integrator, the charge difference between the capacitances being transferred to the differential integrator. A comparator triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator.

Abstract: A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.

Abstract: A pre-driving stage drives one or more Field Effect Transistors in a power stage driving a load. A method for measuring current flowing in the Field Effect Transistors includes: measuring drain to source voltages of the one or more Field Effect Transistor; and measuring an operating temperature of the one or more Field Effect Transistor. The current flowing in the Field Effect Transistors is measured by: calculating the respective on drain to source resistance at the operating temperature as a function of the measured operating temperature and obtaining the current value as a ratio of the respective measured drain to source voltage over the calculated drain to source resistance at the operating temperature.

Abstract: An optoelectronic device includes a backlight panel illuminating a display panel. The backlight panel includes an array of light emitting pixels, each light emitting pixel having at least one subpixel with one or more light emitting diodes positioned on a substrate. The pixel further includes at least one photodetector positioned on the substrate and arranged to detect an amount of reflected light emitted by said subpixel and reflected by the display panel.

Abstract: A system-on-a-chip (SOC) within a package includes a reference generator, a matching circuit, a programmable current generator, a PWM controller, an overvoltage/undervoltage detector receiving a high voltage from a third output pad, a multiplexer passing an input signal to a second output pad, and a SPAD receiving the high voltage. Switching circuitry includes a first switch between the reference generator and an input of the programmable current generator, a second switch between the input of the current generator and the output of the matching circuit, a third switch between the reference generator and an input of the matching circuit, a fourth switch between an output of the current generator and a tap of a ladder within the overvoltage/undervoltage detector, a fifth switch between an output of the current generator and the first output pad, and a sixth switch between the output of the PWM controller and the first output pad.

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

Abstract: An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Abstract: Test stimulus signals applied to at least one circuit under test are produced in a set of test stimulus generators as a function of test stimulus information loaded in test stimulus registers. Loading of the test stimulus information in the test stimulus registers is controlled as a function of test programming information loaded via a programming interface in a respective control register in a set of control registers. The test stimulus generators are activated as a function of the test programming information loaded in said control registers. Test outcome signals received from the at least one circuit under test are used to produce signature comparison signals, which are compared with respective programmable signature reference signals stored in a set of input signature registers, are produced in response to the signature comparison signals produced from the test outcome signals failing to match with the respective reference signals.