Abstract: A method and apparatus for classifying a spatial environment as open or enclosed are provided. In the method and apparatus, one or more microphones detect ambient sound in a spatial environment and output an audio signal representative of the ambient sound. A processor determines a spatial environment impulse response (SEIR) for the audio signal and extracts one or more features of the SEIR. The processor classifies the spatial environment as open or enclosed based on the one or more features of the SEIR.

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract: The present disclosure is directed to a system and method of authenticating a user's face with a ranging sensor. The ranging sensor includes a time of flight sensor and a reflectance sensor. The ranging sensor transmits a signal that is reflected off of a user and received back at the ranging sensor. The received signal can be used to determine distance between the user and the sensor, and the reflectance value of the user. With the distance or the reflectivity, a processor can activate a facial recognition process in response to the distance and the reflectivity. A device incorporating the ranging sensor according to the present disclosure may reduce the overall power consumed during the facial authentication process.

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.

Abstract: Digital signal processing circuitry, in operation, determines, based on accelerometer data, a carry-position of a device. Double-tap detection parameters are set using the determined carry-position. Double-taps are detected using the set double-tap detection parameters. In response to detection of a double-tap, control signals, such as a flag or an interrupt signal, are generated and used to control operation of the device. For example, a device may enter a wake mode of operation in response to detection of a double-tap.

Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

Abstract: A drive signal is applied to a MEMS gyroscope having several intrinsic resonant modes. Frequency and amplitude of mechanical oscillation in response to the drive signal is sensed. At startup, the drive signal frequency is set to a kicking frequency offset from a resonant frequency corresponding to a desired one of the intrinsic resonant modes. In response to sufficient sensed amplitude of mechanical oscillation at the kicking frequency, a frequency tracking process is engaged to control the frequency for the drive signal to sustain mechanical oscillation at the frequency of the desired one of the plurality of intrinsic resonant modes as the oscillation amplitude increases. When the increasing amplitude of the mechanical oscillation exceeds a threshold, a gain control process is used to exercise gain control over the applied drive signal so as to cause the amplitude of mechanical oscillation to match a further threshold. At that point start-up terminates.

Abstract: A microelectromechanical system (MEMS) accelerometer sensor has a mobile mass and a sensing capacitor. To self-test the sensor, a test signal is applied to the sensing capacitor during a reset phase of a sensing circuit coupled to the sensing capacitor. The test signal is configured to cause an electrostatic force which produces a physical displacement of the mobile mass corresponding to a desired acceleration value. Then, during a read phase of the sensing circuit, a variation in capacitance of sensing capacitor due to the physical displacement of the mobile mass is sensed. This sensed variation in capacitance is converted to a sensed acceleration value. A comparison of the sensed acceleration value to the desired acceleration value provides an indication of an error in operation of the MEMS accelerometer sensor if the sensed acceleration value and desired acceleration value are not substantially equal.

Abstract: A microelectromechanical system (MEMS) gyroscope includes a driving mass and a driving circuit that operates to drive the driving mass in a mechanical oscillation at a resonant drive frequency. An oscillator generates a system clock that is independent of and asynchronous to the resonant drive frequency. A clock generator circuit outputs a first clock and a second clock that are derived from the system clock. The drive loop of the driving circuit including an analog-to-digital converter (ADC) circuit that is clocked by the first clock and a digital signal processing (DSP) circuit that is clocked by the second clock.

Abstract: A microelectromechanical system (MEMS) gyroscope sensor has a sensing mass and a quadrature error compensation control loop for applying a force to the sensing mass to cancel quadrature error. To detect fault, the quadrature error compensation control loop is opened and an additional force is applied to produce a physical displacement of the sensing mass. A quadrature error resulting from the physical displacement of the sensing mass in response to the applied additional force is sensed. The sensed quadrature error is compared to an expected value corresponding to the applied additional force and a fault alert is generated if the comparison is not satisfied.

Abstract: A method includes providing a power supply package (PSP) that includes a power supply, an RFID tag, and a power switch, where a control terminal of the power switch is coupled to an output terminal of the RFID tag, and load path terminals of the power switch are coupled between an output terminal of the PSP and a first terminal of the power supply, where a control register of the RFID tag is pre-programmed with a first value such that the RFID tag is configured to generate a first control signal that turns off the power switch; receiving, by the RFID tag, a second value for the control register of the RFID tag; and writing, by the RFID tag, the second value to the control register of the RFID tag such that the RFID tag is configured to generate a second control signal that turns on the power switch.

Abstract: The present disclosure is directed to a method and system for scanning an object or environment with a ranging sensor. The method involves rotating a ranging sensor around a rotation reference point and associating the distances measured with the ranging sensor with rotation measurements from a rotation sensor fixed to the ranging sensor. The associated data is used to populate a data plot or data table to be used to generate three-dimensional models.

Abstract: An electronic device includes a time-of-flight sensor configured to sense a distance between the electronic device and at least one object proximate the electronic device. Processing circuitry is coupled to the time-of-flight sensor and controls access to the electronic device based on the sensed distance. The electronic device may include a digital camera that the processing circuitry controls to perform facial or iris recognition utilizing the sensed distance from the time-of-flight sensor.

Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.