Patents Assigned to STMicroelectronics, Inc.
  • Publication number: 20220293498
    Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 15, 2022
    Applicants: STMicroelectronics S.r.l., STMicroelectronics, Inc.
    Inventors: Fulvio Vittorio FONTANA, Davide Maria BENELLI, Jefferson Sismundo TALLEDO
  • Patent number: 11444759
    Abstract: A method of cryptographically binding a secure element to a host device includes storing host key information in a host key information slot of the secure element and storing binding information in secure memory of the secure element. The binding information is correlated with the host key information. The method includes storing a second secret key within system operational code of the host device. The second secret key is cryptographically correlated with the host key information. The method includes, after storing the binding information and after storing the second secret key, operationally coupling the secure element to the host device, reading, by the host device, the binding information from the secure element, generating, by the host device, the host key information using the binding information and the second secret key, and storing, by the host device, the host key information in a host key information slot of the host device.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 13, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Giuseppe Pilozzi
  • Publication number: 20220285249
    Abstract: A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Aaron CADAG, Frederick ARELLANO, Ernesto ANTILANO, JR.
  • Patent number: 11407098
    Abstract: A device for generating a control signal based on the linear movement of a linear member is provided. The device includes a linear member, a rotatable member, a first inertial measurement unit (IMU) coupled to the rotatable member and a second IMU having a fixed position. The device also includes a processing circuit which uses sensing signals from the IMUS to determine an attitude of the first IMU referenced to the second IMU and generate a control signal based on the attitude.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 9, 2022
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS, INC.
    Inventors: Marco Bianco, Lorenzo Bracco, Mahesh Chowdhary, Roberto Mura, Stefano Paolo Rivolta, Federico Rizzardini
  • Patent number: 11404355
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 2, 2022
    Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Patent number: 11398554
    Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: July 26, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 11398417
    Abstract: Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: July 26, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11397077
    Abstract: The present disclosure is directed to a system and method of controlling a facial recognition process by validating preconditions with a ranging sensor. The ranging sensor transmits a ranging signal that is reflected off of a user's face and received back at the ranging sensor. The received ranging signal can be used to determine distance between the user's face and the mobile device or to determine the reflectivity of the user's face. Comparing the distance to a range of distances corresponding to normal operation of the device or normal reflectivities associated with human skin tones can reduce the number of false positive activations of the facial recognition process. Furthermore, a multiple zone ranging sensor can produce a face depth map that can be compared to a stored face depth map or can produce a reflectivity map that can be compared to a stored face reflectivity map to further increase power efficiency and device security.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: July 26, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Arnaud Deleule, John E. Kvam, Kalyan-Kumar Vadlamudi-Reddy
  • Patent number: 11393774
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 19, 2022
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano
  • Patent number: 11394195
    Abstract: A power supply interface includes a first switch that couples an input terminal to an output terminal. A voltage dividing bridge is coupled to receive a supply potential. A comparator has a first input connected to a first node of the bridge and a second input configured to receive a constant potential. A digital-to-analog converter generates a control voltage that is selectively coupled by a second switch to a second node of the bridge. A circuit control controls actuation of the second switch based on operating mode and generates a digital value input to the converter based on a negotiated set point of the supply potential applied to the input terminal.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 19, 2022
    Assignees: STMicroelectronics (Tours) SAS, STMicroelectronics, Inc.
    Inventors: Mathieu Rouviere, Jeffrey Blauser, Jr., Karl Grange, Mohamed Saadna
  • Publication number: 20220206085
    Abstract: An electronic device includes a magnetometer that outputs magnetometer sensor signals and a gyroscope that outputs gyroscope sensor signals. The electronic device includes a magnetometer calibration module that calibrates the magnetometer utilizing the gyroscope sensor signals. The electronic device generates a first magnetometer calibration parameter based on a Kalman filter process. The electronic device generates a second magnetometer calibration parameter based on a least squares estimation process.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: STMicroelectronics, Inc.
    Inventors: Mahaveer JAIN, Mahesh CHOWDHARY
  • Patent number: 11373322
    Abstract: The present disclosure provides a device and method for depth sensing by utilizing the combination of a ranging sensor and an image sensor. The ranging sensor can accurately detect distance measurement from an object. The image sensor can take images with high resolution of the object. By combining each sensor data from the ranging sensor and the image sensor, accurate depth information with high resolution of the object may be obtained. A structured light having patterned shapes are used in conjunction with the ranging sensor to receive reflected patterned shapes of the object. These reflected patterned shapes are used to analyze distance measurements associated with the specific patterned shapes. These distance measurements from both the ranging sensor and the image sensor is aligned and combined to generate an accurate depth map with high resolution using a processor of an electronic device including the ranging sensor and the image sensor.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 28, 2022
    Assignee: STMicroelectronics, Inc.
    Inventors: Xiaoyong Yang, Chang Myung Ryu, James Kath, Rui Xiao
  • Patent number: 11374111
    Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: June 28, 2022
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Chun-Chen Yeh, Qing Liu, Ruilong Xie
  • Patent number: 11354100
    Abstract: The disclosure describes methods and apparatus for quickly prototyping of a solution developed using one or more sensing devices (e.g., sensors), functional blocks, algorithm libraries, and customized logic. The methods produce firmware executable by a processor (e.g., a microcontroller) on an embedded device such as a development board, expansion board, or the like. By performing these methods on the apparatus described, a user is able to create a function prototype without having deep knowledge of the particular sensing device or any particular programming language. Prototypes developed as described herein enable the user to rapidly test ideas and develop sensing device proofs-of-concept. The solutions produced by the methods and apparatus improve the functioning of the sensor being prototyped and the operation of the embedded device where the sensor is integrated.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: June 7, 2022
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.
    Inventors: Mahesh Chowdhary, Miroslav Batek, Marian Louda
  • Patent number: 11355423
    Abstract: A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 7, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Frederick Arellano, Ernesto Antilano, Jr.
  • Patent number: 11348863
    Abstract: In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In one embodiment, a device includes a die pad, leads that are spaced apart from the die pad, and a semiconductor die on the die pad. The semiconductor die has a first surface and a second surface opposite the first surface. The second surface faces the die pad. An encapsulant is provided on the semiconductor die, the die pad and the leads, and the encapsulant has a first surface opposite the die pad and the leads, and a second surface opposite the first surface. The second surface of the encapsulant extends between the die pad and an adjacent lead. The second surface of the encapsulant is spaced apart from the first surface of the encapsulant by a first distance, and an exposed surface of the die pad is spaced apart from the first surface of the encapsulant by a second distance that is greater than the first distance.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 31, 2022
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Talledo
  • Publication number: 20220140110
    Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.
    Type: Application
    Filed: January 12, 2022
    Publication date: May 5, 2022
    Applicant: STMICROELECTRONICS, INC.
    Inventor: John H. ZHANG
  • Publication number: 20220139845
    Abstract: The present disclosure is directed to a semiconductor package that include a non-conductive encapsulation layer encapsulation an integrated circuit chip, and a conductive encapsulation layer over the non-conductive encapsulation layer. A lead is exposed from the non-conductive encapsulation layer and contacts the conductive encapsulation layer. The conductive encapsulation layer and the lead provide EMI shielding for the integrated circuit chip.
    Type: Application
    Filed: October 25, 2021
    Publication date: May 5, 2022
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Endalicio MANALO, Rennier RODRIGUEZ
  • Patent number: 11320452
    Abstract: A microelectromechanical system (MEMS) accelerometer sensor has a mobile mass and a sensing capacitor. To self-test the sensor, a test signal is applied to the sensing capacitor during a reset phase of a sensing circuit coupled to the sensing capacitor. The test signal is configured to cause an electrostatic force which produces a physical displacement of the mobile mass corresponding to a desired acceleration value. Then, during a read phase of the sensing circuit, a variation in capacitance of sensing capacitor due to the physical displacement of the mobile mass is sensed. This sensed variation in capacitance is converted to a sensed acceleration value. A comparison of the sensed acceleration value to the desired acceleration value provides an indication of an error in operation of the MEMS accelerometer sensor if the sensed acceleration value and desired acceleration value are not substantially equal.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 3, 2022
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.r.l.
    Inventors: Yamu Hu, David McClure, Alessandro Tocchio, Naren K. Sahoo, Anthony Junior Casillan
  • Publication number: 20220128360
    Abstract: A microelectromechanical system (MEMS) gyroscope sensor has a sensing mass and a quadrature error compensation control loop for applying a force to the sensing mass to cancel quadrature error. To detect fault, the quadrature error compensation control loop is opened and an additional force is applied to produce a physical displacement of the sensing mass. A quadrature error resulting from the physical displacement of the sensing mass in response to the applied additional force is sensed. The sensed quadrature error is compared to an expected value corresponding to the applied additional force and a fault alert is generated if the comparison is not satisfied.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics, Inc.
    Inventors: Yamu HU, Deyou FANG, David MCCLURE, Huantong ZHANG, Naren K. SAHOO