Patents Assigned to STMicroelectronics, Inc.
  • Publication number: 20230032490
    Abstract: A robotic device including one or more proximity sensing systems coupled to various portions of a robot body. The proximity sensing systems detect a distance of an object about the robot body and the robotic device reacts based on the detected distance. The proximity sensing systems obtain a three-dimensional (3D) profile of the object to determine a category of the object. The distance of the object is detected multiple times in a sequence to determine a movement path of the object.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 2, 2023
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Cheng PENG, Xiaoyong YANG
  • Patent number: 11569384
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: January 31, 2023
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Pierre Morin
  • Publication number: 20230018529
    Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.
    Type: Application
    Filed: September 20, 2022
    Publication date: January 19, 2023
    Applicant: STMICROELECTRONICS, INC.
    Inventor: John H. ZHANG
  • Patent number: 11557548
    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 17, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Lester Joseph Belalo, Ela Mia Cadag
  • Patent number: 11552007
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 11550531
    Abstract: A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: January 10, 2023
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Benedetto Vigna, Mahesh Chowdhary, Matteo Dameno
  • Publication number: 20230006823
    Abstract: A secure element device that is configured to be cryptographically bound to a host device includes a secure element host key slot configured to store host key information that allows only the host device to control the secure element, a secure memory storing binding information, and limited functionality allowing the binding information to be read from the secure memory by the host device during a binding process. The binding information is cryptographically correlated with the host key information. The host key information is generated by the host device using the binding information read from the secure element and a secret key. The secure element device further includes general functionality only accessible to the host device using the host key information that is generated by the host device. The secure memory includes prevention measures impeding unauthorized entities from obtaining information from the secure memory.
    Type: Application
    Filed: September 7, 2022
    Publication date: January 5, 2023
    Applicant: STMicroelectronics, Inc.
    Inventor: Giuseppe Pilozzi
  • Patent number: 11542152
    Abstract: A cavity type semiconductor package with a substrate and a cap is disclosed. The semiconductor package includes a first semiconductor die coupled to the substrate and a layer of flexible material on a surface of the cap. A trace is on the layer of flexible material. The cap is coupled to the substrate with the layer of flexible material and the trace between the cap and the substrate. A second semiconductor die is coupled to the layer of flexible material and the trace on the cap. The cap further includes an aperture to expose the second semiconductor die to the ambient environment. The layer of flexible material absorbs stress during operation cycles of the package induced by the different coefficient of thermal expansions of the cap and the substrate to reduce the likelihood of separation of the cap from the substrate.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 3, 2023
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Talledo
  • Patent number: 11528407
    Abstract: A method includes dividing a field of view into a plurality of zones and sampling the field of view to generate a photon count for each zone of the plurality of zones, identifying a focal sector of the field of view and analyzing each zone to select a final focal object from a first prospective focal object and a second prospective focal object.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: December 13, 2022
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS, INC., STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Darin K. Winterton, Donald Baxter, Andrew Hodgson, Gordon Lunn, Olivier Pothier, Kalyan-Kumar Vadlamudi-Reddy
  • Patent number: 11515418
    Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 29, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 11507654
    Abstract: A secure engine method includes providing an embedded microcontroller in an embedded device, the embedded microcontroller having internal memory. The method also includes providing a secure environment in the internal memory. The secure environment method recognizes a boot sequence and restricts user-level access to the secure environment by taking control over the secure environment memory. Taking such control may include disabling DMA controllers, configuring at least one memory controller for access to the secure environment, preventing the execution of instructions fetched from outside the secure environment, and only permitting execution of instructions fetched from within the secure environment. Secure engine program instructions are then executed to disable interrupts, perform at least one secure operation, and re-enable interrupts after performing the at least one secure operation.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 22, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Maurizio Gentili, Massimo Panzica
  • Patent number: 11502388
    Abstract: An embodiment electronic device includes a ground plane; and an antenna. The antenna includes a first trace having a first end and a second end, the second end of the first trace being electrically coupled to the ground plane. The antenna also includes a second trace distinct and physically separated from the first trace, the second trace having a first end and a second end, the second end of the second trace being electrically coupled to the ground plane, the first trace and the second trace forming discontinuous portions of the antenna.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: November 15, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Pierre Rizzo, John Coronado, Mohammad Mazooji
  • Publication number: 20220358062
    Abstract: A microcontroller includes a memory, direct memory access (DMA) controllers and a microprocessor. The microprocessor maintains one or more memory protection (MP) configurations to control access to protected memory areas of the microcontroller. In response to a secure service call of an unsecure user-application, the microprocessor executes a state machine which disables interrupt requests, determining whether DMA controller configurations and MP configurations satisfy secure-service criteria. When the secure-service criteria are satisfied, at least one secure operation associated with the secure service call is performed, and memory areas accessed during the execution of the at least one secure operation are cleaned. The interrupt requests are re-enabled and a response to the secure service call is generated.
    Type: Application
    Filed: May 4, 2021
    Publication date: November 10, 2022
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Massimo PANZICA, Maurizio GENTILI
  • Patent number: 11495676
    Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 8, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 11482608
    Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: October 25, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Publication number: 20220333912
    Abstract: The present disclosure is directed to a system and method of controlling a facial recognition process by validating preconditions with a ranging sensor. The ranging sensor transmits a ranging signal that is reflected off of a user's face and received back at the ranging sensor. The received ranging signal can be used to determine distance between the user's face and the mobile device or to determine the reflectivity of the user's face. Comparing the distance to a range of distances corresponding to normal operation of the device or normal reflectivities associated with human skin tones can reduce the number of false positive activations of the facial recognition process. Furthermore, a multiple zone ranging sensor can produce a face depth map that can be compared to a stored face depth map or can produce a reflectivity map that can be compared to a stored face reflectivity map to further increase power efficiency and device security.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Arnaud DELEULE, John E. KVAM, Kalyan-Kumar VADLAMUDI-REDDY
  • Publication number: 20220328632
    Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Applicant: STMICROELECTRONICS, INC.
    Inventor: John H. ZHANG
  • Patent number: 11467180
    Abstract: A distributed computing system for artificial intelligence in autonomously appreciating a circumstance context of a smart device. Raw context data is detected by sensors associated with the smart device. The raw context data is pre-processed by the smart device and then provided to a cloud based server for further processing. At the cloud based server, various sets of feature data are obtained from the pre-processed context data. The various sets of feature data are compared with corresponding classification parameters to determine a classification of a continuous event and/or a classification of transient event, if any, which occur in the context. The determined classification of the continuous event and the transient event will be used to autonomously configure the smart device or another related smart device to fit the context.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: October 11, 2022
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Rajendar Bahl
  • Publication number: 20220320014
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Applicant: STMICROELECTRONICS, INC.
    Inventor: Ian Harvey ARELLANO
  • Patent number: 11453123
    Abstract: A robotic device including one or more proximity sensing systems coupled to various portions of a robot body. The proximity sensing systems detect a distance of an object about the robot body and the robotic device reacts based on the detected distance. The proximity sensing systems obtain a three-dimensional (3D) profile of the object to determine a category of the object. The distance of the object is detected multiple times in a sequence to determine a movement path of the object.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 27, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Cheng Peng, Xiaoyong Yang