Patents Assigned to STMicroelectronics, Inc.
  • Patent number: 10843465
    Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 24, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Murray J. Robinson, Kenneth J. Stewart
  • Patent number: 10840168
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: November 17, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Patent number: 10836167
    Abstract: The present disclosure provides supports for a microfluidic die and one or more additional die including, but not limited to, microfluidic die, ASICs, MEMS devices, and sensors. This includes semi-flexible supports that allow a microfluidic die to be at a 90 degree angle with respect to another die and rigid supports that allow a microfluidic and another die to be in close proximity to each other.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: November 17, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Simon Dodd
  • Patent number: 10824175
    Abstract: Devices, systems, and methods are provided for monitoring air flow through a server using differential pressure measurements. The device includes an external pressure sensor, an internal pressure sensor, and a controller that receives the pressures from the external and internal pressure sensors. The external pressure sensor detects air pressure of the ambient air around a server enclosure, the internal pressure sensor detects air pressure through a server enclosure, and the controller calculates a pressure differential between the pressure from the external pressure sensor and the internal pressure sensor. The controller can then generate a signal based on the pressure differential, the signal optionally controlling a cooling fan, generating an interrupt for the server circuitry, or performing some other action.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 3, 2020
    Assignee: STMicroelectronics, Inc.
    Inventor: Dominique Paul Barbier
  • Patent number: 10823826
    Abstract: A time of flight range detection device includes a laser configured to transmit an optical pulse into an image scene, a return single-photon avalanche diode (SPAD) array, a reference SPAD array, a range detection circuit coupled to the return SPAD array and the reference SPAD array, and a laser driver circuit. The range detection circuit in operation determines a distance to an object based on signals from the return SPAD array and the reference SPAD array. The laser driver circuit in operation varies an output power level of the laser in response to the determined distance to the object.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: November 3, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Xiaoyong Yang, Rui Xiao, Arnaud Deleule
  • Patent number: 10816729
    Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 27, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 10812079
    Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 20, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Chetan Bisht, Harry Scrivener, III
  • Patent number: 10804377
    Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 13, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 10802572
    Abstract: A system may include a motion sensor configured to generate a motion signal in response to a movement of an electronic device, and at least one feature detection circuit configured to determine at least one metric based on the motion signal. The system may further include a classifying circuit configured to determine whether the electronic device is in contact with a human body based on the at least one metric.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 13, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Sankalp Dayal, Mahesh Chowdhary, Mahaveer Jain
  • Patent number: 10796984
    Abstract: The present disclosure is directed to a leadframe package having leads with protrusions on an underside of the leadframe. The protrusions come in various shapes and sizes. The protrusions extend from a body of encapsulant around the leadframe to couple to surface contacts on a substrate. The protrusions have a recess that is filled with encapsulant. Additionally, the protrusions may be part of the lead or may be a conductive layer on the lead. In some embodiments a die pad of the leadframe supporting a semiconductor die also has a protrusion on the underside of the leadframe. The protrusion on the die pad has a recess that houses an adhesive and at least part of the semiconductor die. The die pad with a protrusion may include anchor locks at the ends of the die pad to couple to the encapsulant.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 6, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Raymond Albert Narvadez, Ernesto Antilano, Jr.
  • Patent number: 10783240
    Abstract: A secure engine method includes providing an embedded microcontroller in an embedded device, the embedded microcontroller having internal memory. The method also includes providing a secure environment in the internal memory. The secure environment method recognizes a boot sequence and restricts user-level access to the secure environment by taking control over the secure environment memory. Taking such control may include disabling DMA controllers, configuring at least one memory controller for access to the secure environment, preventing the execution of instructions fetched from outside the secure environment, and only permitting execution of instructions fetched from within the secure environment. Secure engine program instructions are then executed to disable interrupts, perform at least one secure operation, and re-enable interrupts after performing the at least one secure operation.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 22, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Maurizio Gentili, Massimo Panzica
  • Patent number: 10759168
    Abstract: The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Simon Dodd, David S. Hunt, Joseph Edward Scheffelin, Dana Gruenbacher, Stefan H. Hollinger, Uwe Schober, Peter Janouch
  • Patent number: 10763194
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS PTE LTD
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Patent number: 10759169
    Abstract: The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Simon Dodd, David S. Hunt, Joseph Edward Scheffelin, Dana Gruenbacher, Stefan H. Hollinger, Uwe Schober, Peter Janouch
  • Patent number: 10747933
    Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Chetan Bisht, Harry Scrivener, III
  • Patent number: 10749575
    Abstract: A method and near field communications (NFC) system for sensing at least one of an environmental condition or a composition of media in a proximity of the NFC system are provided. In the method and system, a first antenna irradiates an electromagnetic field during a sensor mode. A second antenna detects the electromagnetic field and outputs a voltage representative of the detected electromagnetic field. An NFC controller receives a signal representative of the voltage. The NFC controller determines at least one of the environmental condition or the composition of media based on an association stored in memory between the voltage and the at least one of the environmental condition or the composition of media.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Christophe Henri Ricard, Mohammad Mazooji
  • Patent number: 10748075
    Abstract: Disclosed herein is a method of operating an electronic device. The method includes activating a first sensing device, and determining a first probabilistic context of the electronic device relative to its surroundings. The method includes outputting the first probabilistic context, and determining a confidence measure of the first probabilistic context. Where the confidence measure of the first probabilistic context is below a threshold, the method includes activating a second sensing device, determining a second probabilistic context of the electronic device relative to its surroundings. outputting the second probabilistic context, and determining a confidence measure of the second probabilistic context. Where the confidence measure of the second probabilistic context is above the threshold, the second sensing device is deactivated and the method returns to determining the first probabilistic context.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: August 18, 2020
    Assignees: STMicroelectronics, Inc., STMicroelectronics International N.V.
    Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Kashif R. J. Meer, Indra Narayan Kar, Rajendar Bahl
  • Patent number: 10749031
    Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 18, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 10741698
    Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: August 11, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10731984
    Abstract: A sensor chip includes registers storing and outputting configuration data, an extraction circuit receiving digital data and extracting features of the digital data in accordance with the configuration data, and a classification circuit applying a decision tree to the extracted features to generate a context of an electronic device into which the sensor chip is incorporated relative to its surroundings, the decision tree operating according to the configuration data. The classification unit outputs the context to the registers for storage. The configuration data includes which features for the extraction circuit to extract from the digital data, and a structure for the decision tree. The structure for the decision tree includes conditions that the decision tree is to apply to the at least one extracted feature, and outcomes to be effectuated based upon whether the extracted features meet or do not meet the conditions.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 4, 2020
    Assignee: STMicroelectronics, Inc.
    Inventor: Mahesh Chowdhary