Abstract: A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.

Abstract: In a method for driving electronic devices connected to a vehicle trailer tow connector a trailer electronic device control signal is receiving from a vehicle data communication network. In response to the received control signal, a solid state power control device is switched to connect electrical power to a selected pin of the trailer tow connector. The trailer electronic device control signal may be received from a wiring harness connector connected to a vehicle data communication network. A vehicle trailer tow connector module includes a module housing. A vehicle wiring connector and a trailer wiring connector are coupled to the module housing. A power control circuit is connected to a selected pin in the trailer wiring connector. A controller circuit is coupled to the vehicle wiring connector for receiving communication data from a vehicle data bus, and coupled by control lines to the power control circuit.

Abstract: In a method for producing a control signal for regulating a drive current for driving an LED, a current through the LED is sensed, wherein the LED is driven by a power converter output, and wherein an output voltage of the power converter is proportionately controlled by a control signal. Next, a power supply voltage is sensed. The control signal is produced for the power converter, wherein the control signal is proportional to a difference between a reference voltage and the current through the LED. The control signal is then offset in response to the power supply voltage to reduce the current through the LED as the power supply voltage drops.

Abstract: A wireless system including a plurality of WRAN's operating on different channels identifies and addresses a number of important issues relating to the current CBP mechanism (in D0.3) used for inter-cell discovery and communication. The present invention provides fundamental remedies to respectively resolve these issues. Moreover, an Enhanced Coexistence Beaconing Protocol (CBP) is provided that allows efficient, scalable, and backward-compatible cross-channel inter-cell communications for IEEE 802.22 systems.

Abstract: A semiconductor indicator for quantitatively diagnosing voltage conditions in high power transistor devices is provided. The semiconductor indicator includes a first transistor and a second transistor, where an electrically active periphery of the second transistor is less than an electrically active periphery of the first transistor. The transistors are thermally coupled to one another and may be in close proximity. The second transistor detects the voltage of a node on the first transistor and may be monitored by infrared imaging. The breakdown voltage characteristic of the second transistor may not substantially change as the temperature in the first transistor increases. An optional control circuit monitors and detects the output voltage of the first transistor.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: The bottom mold portion for a transfer molding system is covered with a deformable material. During mold clamping, the deformable material contacts the bottom surface of the packaging substrate on which the integrated circuit die is mounted. Deformation of this relatively soft covering on the bottom mold portion accommodates thickness variations in the packaging substrate, as well as non-planarity of the adhesive layer between the integrated circuit die and packaging substrate in exposed active area integrated circuits.

Abstract: A system and method is disclosed for controlling a height and a planarity of an integrated circuit die. In one advantageous embodiment of the invention, a plurality of patterned metal stops are fabricated on an integrated circuit substrate and covered with die attach material. An integrated circuit die is inserted into the die attach material and placed into a clamping mechanism of a molding machine. The clamping mechanism (1) compresses the die into the die attach material, (2) rotates the die into parallel alignment with the substrate, and (3) pushes the die into contact with the patterned metal stops. In this manner the die height and the die planarity are precisely controlled.

Abstract: A comparison is made in a number of scenarios of a current channel gain setting for a receiver to a threshold. If the current channel gain setting is less than the threshold, then current within at least a portion of the receiver is decreased. In one scenario, the comparison is only made in event that no single tone interferer is detected. In another scenario, the comparison is made to a tolerable single tone blocker threshold, and if greater then current is decreased. In another scenario, the comparison is made to an acceptable intermodulation response rejection threshold, and if greater then current is decreased. In yet another scenario, the comparison is made to an acceptable spurious free dynamic range threshold, and if greater then current is decreased. The portions of the receiver for which current decreases are implemented include a low noise amplifier, mixer, voltage controlled oscillator and variable gain amplifiers.

Abstract: A method includes receiving an activation signal at a semiconductor device and generating an output power signal at the semiconductor device in response to receiving the activation signal. The output power signal has a duty cycle. The method also includes providing the output power signal to a load. The output power signal provides power to the load. An amount of power provided to the load is based on the duty cycle of the output power signal. In addition, the method includes adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.

Abstract: A self-coexistence window reservation protocol for a plurality of Wireless Regional Area Network (WRAN) cells operating in a WRAN over a plurality of channels includes a sequence of self-coexistence windows that uniquely identifies a transmission period for each WRAN cell. A self-coexistence window reservation protocol is included within the first packet of a Coexistence Beaconing Protocol period identifying when each WRAN cell associated with a particular channel will transmit. When not actively transmitting, a WRAN cells remains in a passive, receiving mode to accept data. As the transmissions of each WRAN cell operating on a particular channel are scheduled, contention for a transmission period is eliminated.

Abstract: The invention relates generally to communication systems and in particular to radio frequency (RF) architectures. Some embodiments of the invention are directed towards a multi-channel inter-BS communication system. The multi-channel inter-BS communication system includes a plurality of co-existing wireless regional area network (WRAN) cells, wherein each of the plurality of co-existing WRAN cells includes a plurality of data frames and at the end of each of the plurality of data frames is a slotted co-existence window. Additional embodiments of the invention include CB frames, fixed-slot host scheduling and modulo scheduling.

Abstract: In an integrated free-fall detection device for a portable apparatus an acceleration sensor generates acceleration signals correlated to the components of the acceleration of the portable apparatus along three detection axes. A dedicated purely hardware circuit connected to the acceleration sensor generates a free-fall detection signal in a continuous way and in real-time. The free-fall detection signal has a first logic value in the event that the acceleration signals are simultaneously lower than a respective acceleration threshold, and is sent to a processor unit of the portable apparatus as an interrupt signal to activate appropriate actions of protection for the portable apparatus. Preferably, the acceleration sensor and the dedicated purely hardware circuit are integrated in a single chip and the acceleration sensor is made as a MEMS.

Abstract: A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control flags, executable instruction codes, and tag information. In the event that a comparison against the current program counter succeeds, then execution is altered as required per the control flags. If no comparison match is made, then execution of the instruction that was accessed by the program counter is executed.

Abstract: A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region. Thereafter, a film containing a second type dopant is deposited in the front and back isolation wall trenches. In the conduction region on the back surface, conduction region trenches are formed inside the perimeter of the isolation wall trenches. A first type dopant is deposited in the conduction region trenches. The dopants are diffused from the conduction region trenches and isolation wall trenches to form a first conductivity type conduction region structure and a second conductivity type isolation wall.

Abstract: An integrated circuit temperature sensor includes a sensor to determine whether the integrated circuit is currently exposed to a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected if the sensor indicates exposure to the relatively low temperature or, a measured delta voltage across the base-emitter of the bipolar transistor is selected if the sensor indicates exposure to the relatively high temperature. The voltage across the base-emitter is compared against a first reference for determining exposure to a too cold condition or the selected measured delta voltage across the base-emitter is compared against a second reference for determining exposure to a too hot condition. In a test mode, the measured delta voltage across the base-emitter and/or the measured voltage across the base-emitter are scaled.

Abstract: An image processing system recovers 3-D depth information for pixels of a base image representing a view of a scene. The system detects a plurality of pixels in a base image that represents a first view of a scene. The system the determines 3-D depth of the plurality of pixels in the base image by matching correspondence to a plurality of pixels in a plurality of images representing a plurality of views of the scene. The system then traces pixels in a virtual piecewise continuous depth surface by spatial propagation starting from the detected pixels in the base image by using the matching and corresponding plurality of pixels in the plurality of images to create the virtual piecewise continuous depth surface viewed from the base image, each successfully traced pixel being associated with a depth in the scene viewed from the base image.

Abstract: A method for generating a temperature-compensated control signal is provided. The method includes receiving a constant control signal. A temperature-compensated control signal is generated based on the constant control signal. The temperature-compensated control signal is provided to a variable gain amplifier. The temperature-compensated control signal is operable to cause the variable gain amplifier to function independently of temperature.

Abstract: A design method for an integrated circuit adds spare cells in a System-on-Chip to allow for Engineering Change Orders (ECOs) to be performed at a later stage in the design. This method can be used to provide a second version of the chip having minimal alterations performed in a short cycle time. The spare cells can be divided into combinational and sequential cells. There is an optimum spread of combinational cells in the design for post placement repairs of the chip with just metal layer changes. The method takes into account the drive strength of the spare cells as the main factor in their placement on the chip.

Abstract: An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node.