Abstract: A device for correlating trend data with respect to a patient's weight ankle displacement can identify conditions indicative of congestive heart failure. A weight scale or similar device coupled with imaging mechanism operable to measure ankle displacement collects a plurality of measurements over a period of time. Over time trend analysis of both the patient's weight and the ankle displacement measurements can be obtained and compared to identify whether over a particular sample period an increase in a patient's ankle displacement is or is not correlated with an increase in the patient's weight. When an increase in ankle displacement is identified as not correlating to a corresponding change in the patient's weight an alert can be issued of conditions indicative of congestive heart failure.

Abstract: A microfabricated structure and method of making that includes forming a first layer of material on a substrate, forming patterned sacrificial material having a predetermined shape on the first layer of material, and forming a second layer of material over the first layer and the patterned sacrificial material, which is then removed to form an encapsulated cavity. Ideally, the first and second layers are formed of the same type material. A structural support layer can be added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

Abstract: A system on chip (SoC) integrated circuit includes a plurality of computational blocks. A modular data transfer architecture interconnects the computational blocks for intra-chip communications. The computational blocks include an initiator block and a target block, with the initiator block originating a data communication having a global address associated with the target block. The modular data transfer architecture includes a first peripheral module having an initiator port connected to the initiator block to receive the data communication and a second peripheral module having a target port connected to the target block. A first port mapper within the first peripheral module maps the global address to a first peripheral module target port along a data path towards the second peripheral module. A second port mapper within the second peripheral module maps the global address to the target port connected to the target block.

Abstract: An integrated cell for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the sign of the difference invariable.

Abstract: In a method for driving electronic devices connected to a vehicle trailer tow connector a trailer electronic device control signal is receiving from a vehicle data communication network. In response to the received control signal, a solid state power control device is switched to connect electrical power to a selected pin of the trailer tow connector. The trailer electronic device control signal may be received from a wiring harness connector connected to a vehicle data communication network. A vehicle trailer tow connector module includes a module housing. A vehicle wiring connector and a trailer wiring connector are coupled to the module housing. A power control circuit is connected to a selected pin in the trailer wiring connector. A controller circuit is coupled to the vehicle wiring connector for receiving communication data from a vehicle data bus, and coupled by control lines to the power control circuit.

Abstract: A thermally conductive ball grid array (BGA) package for integrated circuits having improved ground path employs a printed circuit substrate. The substrate has an array of solder balls disposed on the bottom side. There is an opening in the substrate corresponding to the integrated circuit die. A grounding ring covers the vertical walls of the opening and includes an upper ground collar on the top side of the substrate and a lower ground collar on the bottom side of the substrate. A thermally and electrically conductive heat spreader is attached to the lower ground collar on the bottom side of the BGA package, covering the opening in the substrate. The integrated circuit die is mounted on the heat spreader, with the active side up, within the opening in the substrate. Ground pads on the active side of the die are attached to the upper ground collar by wire bonds, to provide a continuous ground path from the ground pads to the heat spreader.

Abstract: A subpixel interpolator includes an input memory capable of storing video information formed from full pixels. The subpixel interpolator also includes at least one interpolation unit capable of performing subpixel interpolation to generate half-pixels and quarter-pixels in parallel. Multiple half-pixels and multiple quarter-pixels are generated concurrently during the subpixel interpolation. In addition, the subpixel interpolator includes an output memory capable of storing at least some of the full pixels, half-pixels, and quarter-pixels. In some embodiments, the at least one interpolation unit includes a horizontal half-pixel interpolation unit, two vertical half-pixel interpolation units, and a quarter-pixel interpolation unit, all of which may operate in parallel. In particular embodiments, the interpolation units are formed from adders and shifters and do not include any multipliers.

Abstract: A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as for example a high-ohmic poly resistor. The method transfers a pattern defined by a mask onto the screening layer by selectively removing portions of the screening layer in accordance with the pattern. Portions of the auxiliary layer that are not protected by the screening layer are removed using a plasma gas selective to the auxiliary layer material, without removing the area of the auxiliary layer that overlays the portion of the circuit component, thereby protecting the circuit component from the plasma gas via the screening layer and auxiliary layer.

Abstract: An embodiment of a network of extendable computer resources creates a virtual computing environment for a remote client. The network allocates at least some of the extendable computer resources to the virtual computing environment and compressively represents video output information of the virtual computing environment as an encoded data stream. The encoded data stream is communicated to the remote client, and input information to control the resources allocated to the virtual computing environment is received from the remote client. An embodiment of a local computing client receives a multiframe motion picture stream of encoded signals that represent the video output of a virtual computing environment hosted by a remote computer source. The local computing client decodes the motion picture stream, accepts input information operable to control the virtual computing environment, and communicates the input information to the remote computer source.

Abstract: A system of detecting biometric and non-biometric, standard smart card devices includes a smart card host and smart card device reader, which is operable for receiving an Answer to Reset signal and determining whether the smart card device comprises a biometric or non-biometric, standard smart card device. If a biometric smart card device is detected, the smart card reader is operable for applying power used for standard smart card device operation to a first contact and applying power used by a biometric circuit to a second contact, and if a non-biometric, standard smart card device is detected, applying power only to the first contact.

Abstract: The CPU breaks a digital still image file down into multiple sub-picture files. Each sub-picture file is treated as an MPEG video frame and is used to construct an MPEG video stream. An MPEG processor then processes the MPEG video stream. The MPEG processor decodes the video stream and scales each sub-picture down to fit a monitor or television upon which the still image is to be displayed. Each scaled sub-picture is stored in a display buffer but is not displayed until the entire MPEG video stream is decoded.

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Abstract: A first device transmits data over a first branch of a communications link toward a second device. That second device loops the received data pattern back over a second branch of the communications link. A bit error rate of the looped back data pattern is determined and a pre-emphasis applied to the transmitted data pattern is adjusted in response thereto. The first device further perturbs the data pattern communications signal so as to increase the bit error rate. The pre-emphasis is adjusted so as to reduce the determined bit error rate in the looped back data pattern in the presence of the perturbation. The steps for perturbing the signal and adjusting the pre-emphasis are iteratively performed, with the perturbation of the signal increasing with each iteration and adjustment of the pre-emphasis being refined with each iteration. The signal is perturbing by injecting modulation jitter into the signal (increasing each iteration) and adjusting amplitude of the signal (decreasing each iteration).

Abstract: Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer.

Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages.

Abstract: An embodiment for manufacturing an electronic circuit forms at least one first structure on a semiconductor substrate, determines at least one electrically defined characteristic of the at least one first structure, selects a reticle corresponding to the measured characteristic, and forms at least one additional structure on the semiconductor substrate with the selected reticle.

Abstract: In one aspect, a method of making an apparatus includes forming a thin-film battery; affixing a device to the thin-film battery while the thin-film battery is in a substantially discharged state; and subjecting the thin-film battery to a high temperature that exceeds a temperature rating of the thin film battery before the thin-film battery is charged.

Abstract: A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.

Abstract: Methods and systems are described for discovering network topology in a multimedia network. Further the invention describes methods and systems for establishing synchronization between multiple nodes in a multimedia network. Also, disclosed are message transmission systems and methodology using relative path addressing to guide and direct messages in a multimedia network.

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 ? to 500 ?, and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 ?m.