Abstract: A burst error limiting symbol detector system includes a symbol detector circuit responsive to a corrected sample signal for detecting multilevel or multidimensional symbols encoded in the corrected sample signal with reference to a plurality of associated thresholds. A feedback equalizer circuit provides a feedback equalizer signal for cancelling undesired distortion in an input signal. A summing circuit is responsive to the input signal and the feedback equalizer signal to provide the corrected sample signal to the symbol detector circuit. A feedback modification circuit is responsive to the corrected sample being within one of a plurality of valid symbol windows to feed back the detected symbol to the feedback equalizer and is responsive to the corrected sample being within one of plurality of marginal threshold windows to feed back a corresponding intermediate value to the feedback equalizer.

Abstract: Moderately accurate closed loop speed control of a universal motor is attained without the need for any type of speed sensor. Motor armature (across the brushes) voltage is sensed and supplied to a control circuit for processing along with sensed motor current and zero-crossing information. Integration of the motor armature voltage provides a value which is related to current motor speed. By adjusting the gating angle for triac actuation, the armature voltage integral can be maintained at a desired value associated with a desired motor speed. The sensed motor current is also integrated to provide a speed droop compensation value that is added to the desired value, and the gating angle for triac actuation is adjusted to move the armature voltage integral value to approach the summed value of the speed droop compensation value and desired value.

Abstract: A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the substrate. The thin film power transistor further includes a dielectric layer, at least a portion of which is disposed between (i) the gate and (ii) the first and second doped regions. In addition, the thin film power transistor includes a plurality of contacts contacting the plurality of first doped regions, where the plurality of first doped regions forms a source and a drain of the thin film power transistor. The first doped regions could represent n-type regions (such as N? regions), and the second doped region could represent a p-type region (such as a P? region). The first doped regions could also represent p-type regions, and the second doped region could represent an n-type region.

Abstract: An apparatus is provided that includes a light source, an array of light-reflecting devices, and a processor for positioning the light-reflecting devices so as to display an image on the display screen. Each of the light-reflecting devices selectively reflects the light from the light source onto a corresponding pixel of a display screen. The processor positions a first of the light-reflecting devices such that light from the light source is reflected by the first light-reflecting device onto a first pixel of the display screen, which is different than the pixel of the display screen that corresponds to the first light-reflecting device.

Abstract: A power-on reset circuit. The power-on reset circuit includes a switch, a current source coupled between a first potential and a switch first contact; a resistive device having a resistive-device first contact coupled to the first potential; a first module coupled between a second potential and a switch second contact; a second module coupled between the second potential and resistive-device second contact; and an inverter having an inverter input coupled to the resistive-device second contact. Current through the second module mirrors current through the first module. If a first mirrored potential of the second potential present on a switch control contact is greater than a preselected value, the switch first contact is coupled to the switch second contact. Otherwise, the switch first contact is decoupled from the switch second contact.

Abstract: A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region. Thereafter, a film containing a second type dopant is deposited in the front and back isolation wall trenches. In the conduction region on the back surface, conduction region trenches are formed inside the perimeter of the isolation wall trenches. A first type dopant is deposited in the conduction region trenches. The dopants are diffused from the conduction region trenches and isolation wall trenches to form a first conductivity type conduction region structure and a second conductivity type isolation wall.

Abstract: An apparatus and method is provided that reduces the propagation delay in a conductor carrying an electrical signal from a first area of a circuit to a second area of the circuit. The conductor is fabricated to include a first conductor extending from the first area to the second area. The conductor also includes a second conductor extending substantially parallel and along the first conductor and electrically connected to the first conductor. A third and additional conductors may also be used which extend substantially parallel and along the first conductor and are electrically connected to the first conductor. The additional second conductor (and any additional conductors) reduces the capacitance of the conductor thereby reducing the propagation delay in the conductor (increasing the speed of the signal). The additional conductor(s) effectively “shield” the first conductor from some capacitance that the first conductor would normally “see” without the use of such additional conductors.

Abstract: A radiometer sensor includes a target plate and a micro-mechanical spring which supports the target plate above a base support. This construction allows for displacement of the target plate in a direction perpendicular to the base support in response to radiation which is received by a top surface of the target plate. The sensor is enclosed within a housing that defines a sealed interior chamber within which a vacuum has been drawn. The target plate preferably is non-deformable in response to received radiation. Capacitive or piezoelectric sensors are provided to detect the displacement of the target plate, and the measured displacement is correlated to determine a received radiation level. Radiometer sensor output signals are quantized and signal processed so as to make a radiation level determination.

Abstract: In a communication receiver having a variable gain amplifier and an automatic gain controller, the automatic gain controller is operable to measure values of a system performance parameter indicative of the performance of the communication system, determine a statistical value of the system performance parameter, and adjust the variable gain of the amplifier in response to the statistical value to maintain the statistical value in a control range.

Abstract: There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor; 2) an instruction execution pipeline comprising N processing stages, where each processing stage performs one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; and 3) at least one mapping register associated with at least one of the N processing stages, wherein the at least one mapping register stores mapping data that may be used to determine a physical register associated with an architectural stack register accessed by the pending instruction.

Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

Abstract: The invention relates to a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data are grouped into elements of a finite field. Input elements of said input data are modified by a transform generating output elements of the output data, such that a current output element is a linear combination of a current input element and at least one previous output element. A multiplier applied to at least one previous output element is a non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform, is selected such that the output elements resulting from the transform tend to have the desired property.

Abstract: A method includes generating an output signal at a transmitter using an input signal. The method also includes providing the output signal for communication over a communication link. The method further includes identifying a return signal by at least partially removing from the output signal at least one of: the communicated signal and base line wander. In addition, the method includes establishing a synthesized impedance to the return signal.

Abstract: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.

Abstract: A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond pad that covers and fills the substrate cavity. The wire bond pad also has portions that form a wire bond cavity for receiving the ball bond. The ball is wirebonded to the sides and bottom of the wire bond cavity. The sides of the wire bond cavity provide additional strength to the bond to resist shear and tensile forces that may act on the wire.

Abstract: Counter-clockwise and clockwise quadrant transitions are detected and accumulated with respect to a received complex signal over a certain time period. These transitions may then be compared in order to obtain information indicative of both a magnitude and phase of a carrier frequency error for the received signal. Additionally, zero-crossings of the received complex signal over the same certain time period are detected and accumulated. The accumulated crossings provide information indicative of frequency offset magnitude. The determined magnitude and phase of the frequency error may then be used to adjust a local oscillator frequency to provide for improved receiver performance.

Abstract: An apparatus and method are provided to accelerate error diffusion for color halftoning for embedded applications. High performance is achieved by utilizing functional parallelism within the halftoning error diffusion process, including exploiting data parallelism in different color planes, reducing the number of memory accesses to the error buffer, accelerating the computation by using a parallel instruction set, and improving the throughput of the system by implementing pipelined architecture. A halftoning coprocessor architecture can implement the foregoing. The architecture can be optimized for high performance, low complexity and small footprint. The coprocessor can be incorporated into embedded systems to accelerate the performance of error diffusion halftoning therein.

Abstract: A six field address scheme identifies both the originating point and the endpoint of a data frame enabling multiple hop forwarding through a plurality of intermediate mesh points in a wireless mesh network. Data frames originating or ending at a point outside of the wireless mesh network access the wireless network at a mesh access point using a legacy address scheme. The legacy address schemes are converted to a six address scheme using a proxy address table at the access point. Each mesh access point includes not only a routing table but a proxy address table as well as enabling the mesh access point, and/or mesh portal points, to convert address schemes having less than six address fields to the six field format. Subsequent to the conversion, mesh points within the wireless mesh network need only the routing table to facilitate the forwarding of the data frame.

Abstract: A six field address scheme identifies both the originating point and the endpoint of a data frame enabling multiple hop forwarding though a plurality of intermediate mesh points in a wireless mesh network. Data frames originating or ending at a point outside of the wireless mesh network access the wireless network at a mesh access point using a legacy address scheme. The legacy address schemes are converted to a six address scheme using a proxy address table at the access point. Each mesh access point includes not only a routing table but a proxy address table as well as enabling the mesh access point, and/or mesh portal points, to convert address schemes having less than six address fields to the six field format. Subsequent to the conversion, mesh points within the wireless mesh network need only the routing table to facilitate the forwarding of the data frame.

Abstract: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.