Patents Assigned to STMicroelectronics, Inc.
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Publication number: 20080198678Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.Type: ApplicationFiled: February 11, 2008Publication date: August 21, 2008Applicant: STMicroelectronics, Inc.Inventors: David C. McClure, Mark A. Lysinger, Mehdi Zamanian, Francois Jacquet, Philippe Roche
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Publication number: 20080198679Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages.Type: ApplicationFiled: February 13, 2008Publication date: August 21, 2008Applicant: STMicroelectronics, Inc.Inventors: Mark A. Lysinger, David C. McClure, Francois Jacquet
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Publication number: 20080198220Abstract: A compound camera system for generating an enhanced virtual image having a large depth-of-field. The compound camera system comprises a plurality of component cameras for generating image data of an object and a data processor for generating the enhanced virtual image from the image data. The data processor generates the enhanced virtual image by generating a first component virtual image at a first depth plane, generating a second component virtual image at a second depth plane, and inserting first selected pixels from the first component virtual image into enhanced the virtual image and inserting second selected pixels from the second component virtual image into the enhanced virtual image.Type: ApplicationFiled: December 20, 2007Publication date: August 21, 2008Applicant: STMicroelectronics, Inc.Inventors: George Q. Chen, Li Hong, Peter McGuinness
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Publication number: 20080201590Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.Type: ApplicationFiled: April 28, 2008Publication date: August 21, 2008Applicant: STMICROELECTRONICS, INC.Inventors: Davide Rizzo, Osvaldo Colavin
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Patent number: 7413129Abstract: A USB device includes first and second communications ports and a processor operable for configuring the first communications port for connecting to a USB host and configuring the second communications port as a USB master connecting to a USB slave device. The processor can be formed as a USB device controller operatively connected to the first communications port and USB On-The-Go device controller operatively connected to a second communications port for creating a point-to-point connection to the USB slave device.Type: GrantFiled: September 30, 2004Date of Patent: August 19, 2008Assignee: STMicroelectronics, Inc.Inventor: Serge Fruhauf
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Publication number: 20080191917Abstract: A digital-to-analog converter, in response to a digital signal, selectively taps a resistor string to generate an analog output and selectively shunts around resistors in the string to voltage shift the analog output. If two supply voltage sets are present, two strings are provided. A mutually exclusively selection of outputs is made to select a source of the analog output. An integrated circuit temperature sensor uses the converter and includes a sensing circuit that determines exposure to one of a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected in low temperature exposure and compared against a first reference for a too cold temperature condition. Alternatively, a measured delta voltage across the base-emitter is selected in high temperature exposure and compared against a second reference voltage for a too hot temperature condition. Through the comparisons, a temperature exposure detection is made.Type: ApplicationFiled: January 28, 2008Publication date: August 14, 2008Applicant: STMicroelectronics, Inc.Inventors: David C. McClure, Sooping Saw
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Patent number: 7412369Abstract: There is disclosed an apparatus for designing and optimizing a memory for use in an embedded processing system. The apparatus comprises: 1) a simulation controller for simulating execution of a test program to be executed by the embedded processing system; 2) a memory access monitor for monitoring memory accesses to a simulated memory space during the simulated execution of the test program, wherein the memory access monitor generates memory usage statistical data associated with the monitored memory accesses; and 3) a memory optimization controller for comparing the memory usage statistical data and one or more predetermined design criteria associated with the embedded processing system and, in response to the comparison, determining at least one memory configuration capable of satisfying the one or more predetermined design criteria.Type: GrantFiled: June 9, 2000Date of Patent: August 12, 2008Assignee: STMicroelectronics, Inc.Inventor: Vidyabhusan Gupta
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Patent number: 7411433Abstract: A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.Type: GrantFiled: December 15, 2004Date of Patent: August 12, 2008Assignee: STMicroelectronics, Inc.Inventors: David Charles McClure, Rong Yin
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Publication number: 20080188077Abstract: A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier layer (such as those overlying interlevel dielectric regions) are removed first, exposing the tungsten under those regions to removal, while protective barrier layer regions over lower topological regions (such as openings within the interlevel dielectric) remain to prevent chemical attack of underlying tungsten. CMP patterned tungsten is thus substantially planar with the interlevel dielectric without dishing, even in large area tungsten structures such as MOS capacitor structures.Type: ApplicationFiled: April 9, 2008Publication date: August 7, 2008Applicant: STMICROELECTRONICS, INC.Inventors: Charles R. Spinner, Rebecca A. Nickell, Todd H. Gandy
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Publication number: 20080180047Abstract: Disk drive spindle jitter is comprised of electrical noise, error due to pair pole asymmetry, and random disk speed variances. Error caused by pair pole asymmetry can be identified and compensated for by detecting over a single rotation of a rotor a plurality of zero cross signals. These signals can be statistically analyzed over a period of a plurality of revolutions of the rotor so as to identify the systematic error caused by pair poles. Once identified, this pair pole error can be used to modify zero cross signals and/or modify commutation signal driving the disk so as to arrive at a more accurate determination of disk speed and to precisely control the speed of the disk.Type: ApplicationFiled: January 25, 2008Publication date: July 31, 2008Applicant: STMicroelectronics, Inc.Inventor: Frederic Bonvin
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Patent number: 7405740Abstract: A method is provided for scaling a source image to produce a destination image. According to the method, a local context metric is calculated from a local portion of the source image. A convolution kernel is generated from a plurality of available convolution kernels based on the calculated local context metric, and the generated convolution kernel is used to generate at least one pixel in the destination image. Also provided is an image scaling device that receives pixels of a source image and outputs pixels of a scaled destination image. The image scaling device includes a context sensor, a kernel generator, and a scaler. The context sensor calculates a local context metric based on local source image pixels, and the kernel generator generates a current convolution kernel from a plurality of available convolution kernels based on the local context metric calculated by the context sensor.Type: GrantFiled: March 27, 2000Date of Patent: July 29, 2008Assignee: STMicroelectronics, Inc.Inventor: Charles F. Neugebauer
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Patent number: 7402454Abstract: An integrated circuit die having an active area that must remain exposed after packaging is secured by a compliant die attachment by which the integrated circuit die is held in position within a transfer mold during encapsulation. The compliant die attachment may comprise a flexible, compressible tape having pressure-sensitive adhesive, alone or with a rigid substrate support, or a compliant adhesive preferably applied only around a periphery of the die attach area. Deformation of the compliant die attachment under mold clamping pressure allows complete contact of the mold with the active area, preventing bleeding of the encapsulating material under the edge of a mold portion onto the active area.Type: GrantFiled: December 14, 2006Date of Patent: July 22, 2008Assignee: STMicroelectronics, Inc.Inventors: Tiao Zhou, Michael J. Hundt
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Publication number: 20080169951Abstract: A transmitter includes a plurality of devices which processes a transmit signal. Examples of such devices include a variable gain amplifier, a power amplifier and/or a modulator. Some other these devices are gain controllable. Some of these devices are bias controllable. Each controllable device receives at least one analog control signal (gain/bias) which sets operation of the controllable device. A logic circuit receives a specification of the analog control signal and generating a digital control signal based thereon. A digital-to-analog converter circuit converts the digital control signal to the analog control signal for application to the controllable device.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Applicant: STMicroelectronics, Inc.Inventors: Ivan Krivokapic, Lun Bin Huan
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Publication number: 20080165754Abstract: In order to satisfy the conflicting requirements for spectrum sensing and QoS of data transmission, it is highly desirable for a cognitive radio system, e.g. IEEE 802.22 WRAN, to perform spectrum sensing and data transmission simultaneously. Embodiments of the invention address critical issues of self-interference generated from a transmission unit to the co-located sensing unit when the simultaneous sensing and data transmission technique is applied. A number of interference mitigation techniques are described and analyses are given.Type: ApplicationFiled: December 28, 2007Publication date: July 10, 2008Applicant: STMicroelectronics, Inc.Inventor: Wendong Hu
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Publication number: 20080165831Abstract: A Dynamic Frequency Hopping Community (DFH Community) is formed from a plurality of Wireless Regional Area Network (WRAN) cells wherein each of the plurality of WRAN cells within the DFH Community is a one-hop neighbor of the leader cell. The leader cell sets and distributes a hopping pattern for use among the WRAN cells based on, in part, the number of usable channels and whether a WRAN cell is shared by two groups in the DFH Community.Type: ApplicationFiled: January 4, 2008Publication date: July 10, 2008Applicant: STMicroelectronics, Inc.Inventors: Liwen Chu, Wendong Hu, George A. Vlantis
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Patent number: 7397097Abstract: A released beam structure fabricated in trench and manufacturing method thereof are provided herein. One embodiment of a released beam structure according to the present invention comprises a semiconductor substrate, a trench, a first conducting layer, and a beam. The trench extends into the semiconductor substrate and has walls. The first conducting layer is positioned over the walls of the trench at selected locations. The beam is positioned with the trench and is connected at a first portion thereof to the semiconductor substrate and movable at a second portion thereof. The second portion of the beam is spaced from the walls of the trench by a selected distance. Therefore, the second portion of the beam is free to move in a plane that is perpendicular or parallel to the surface of the substrate, and could be deflected to electrically contact with the walls of the trench in response to a predetermined acceleration force or a predetermined temperature variation applied on the beam structure.Type: GrantFiled: November 25, 2003Date of Patent: July 8, 2008Assignee: STMicroelectronics, Inc.Inventors: Richard A. Blanchard, Joseph C. McAlexander
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Patent number: 7398066Abstract: A method and apparatus for recovering a data symbol from a communication signal in which the communication signal is processed to produce a baseband waveform that is then sampled to obtain a channel sequence. The channel sequence is decoded to obtain an estimate of the data symbol together with a measure of the reliability of the data symbol. The processing of the communication signal is adjusted dependent upon the measure of the reliability of the data symbol. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.Type: GrantFiled: November 30, 2004Date of Patent: July 8, 2008Assignee: STMicroelectronics, Inc.Inventor: Gregory Proehl
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Patent number: 7389013Abstract: Connection between optical fibers and optical components within a semiconductor substrate. A lens is created at the front of a semiconductor substrate. A tapered hole is created in the back of the substrate exposing part or all of the surface of the lens. An optical component is formed or affixed at the front surface of the substrate. A volume of transparent adhesive is placed in the hole, followed by an optical fiber, which is thus coupled to the surface of the lens. A light guide is created on the front of the substrate overlying the lens to direct optical signals between the optical fiber inserted in the tapered hole and the optical component on the surface of the substrate.Type: GrantFiled: September 30, 2004Date of Patent: June 17, 2008Assignee: STMicroelectronics, Inc.Inventors: Ming Fang, Larry R. Tullos, Hai Ding
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Patent number: 7385433Abstract: According to the invention a well-switching arrangement, with a semiconductor circuit including a switch having an input terminal, an output terminal and a body region and at least one comparator having a first input coupled to at least one of the terminals and a second input coupled to a positive voltage rail, and logic coupled to an output of the comparator and responsive to the output to selectively couple the body-well region to one of the terminals or to the positive voltage rail.Type: GrantFiled: March 18, 2005Date of Patent: June 10, 2008Assignee: STMicroelectronics, Inc.Inventor: Michael J. Callahan, Jr.
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Patent number: 7386581Abstract: A single bit FIR filter that minimizes computation time by pre-storing outputs or portions of outputs for accumulation and output.Type: GrantFiled: December 31, 2003Date of Patent: June 10, 2008Assignee: STMicroelectronics, Inc.Inventor: Carson H. Zirkle