Abstract: A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, working in conjunction with the host processor, receives data, including any preselected address fields. The network device includes a plurality of ports. Each port includes a FIFO receive memory for receiving at least a first portion of a frame. The first portion of the frame includes data having the preselected address fields. A direct memory access unit transfers a burst of data from the FIFO receive memory to the shared system memory. A communications processor selects the amount of data to be transferred from the FIFO receive memory based on the desired address fields to be analyzed by the host processor.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.

Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.

Abstract: A method for providing cascaded trie-based network packet search engines is provided. A search command is received at one of the network packet search engines. The search command comprises a specific search key. A determination of a longest prefix match based on the specific search key is made at the network packet search engine. A determination is made at the network packet search engine regarding whether the longest prefix match comprises an overall longest prefix match among the cascaded network packet search engines such that any of the cascaded network packet search engines may comprise the overall longest matching prefix independently of position relative to the other cascaded network packet search engines.

Abstract: A bonding pad arrangement for an integrated circuit includes a bonding pad fabricated on a bonding area to enable bonding. A first ESD resistor is fabricated adjacent the bonding area, and at least a second ESD resistor is fabricated adjacent the first ESD resistor and the bonding area. The bonding pad extends beyond the bonding area to connect to the first ESD resistor and to the at least second ESD resistor, thereby providing at least two input ESD circuits for at least one current consuming electronic circuit from the single bonding pad.

Abstract: Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source operand is true. The predicate bit, if any, of the destination register is set to the logical AND of the source registers' predicates. Similarly, in a non-programmable processor synthesized with predicated operand support, an operator will perform the associated function depending on the state of inputs' predicates. The output predicate is evaluated as the logical AND of the inputs' predicates. An additional bit for each data register, a change in the semantics of the instructions to include predication, and a few additional instructions to save and restore register predicate bits and to specifically set or reset a register's predicate bit are required.

Abstract: The present disclosure provides a system for providing a security and method of providing an enhanced security booting environment. The system and method includes a basic input/output system (BIOS) stored in memory. The system and method also includes a counter embedded in the memory configured to monitor the number of times each block of the memory has been written. This information could be used with existing error detection mechanisms to improve the ability to detect unintended write operations.

Abstract: An integrated circuit for a smart card in accordance with an exemplary embodiment includes a transceiver and a processor for communicating with a host device via the transceiver and performing a plurality of smart card applications. Moreover, the processor may cooperate with the host device to perform an enumeration based upon at least one default descriptor, and generate a look-up table for allocating data to respective smart card applications based upon the enumeration. Furthermore, the processor may also detect a system event and, responsive to the system event, cooperate with the host device to perform a new enumeration based upon at least one alternate descriptor and generate a new look-up table based thereon.

Abstract: An image matching method and system for use with multiple images of a scene captured from different angles. Image matching is performed by identifying a plurality of segments within at least two images, determining an initial disparity values for pixels in the images and then determining initial disparity planes for the segments by fitting a plane to initial disparity values for the segments. A refined disparity plane set is created by iteratively refitting the disparity planes by using various fitting cost functions and weighted linear systems. A labeling of each segment to a disparity plane is made by minimizing a global energy function that includes energy terms for segment to disparity plane matching as well as penalizing disparity plane discontinuities between adjacent image segments.

Abstract: A fully automated ASIC style domino synthesis flow is provided for mapping a digital logic design onto a domino logic library. The input to the flow is the same as for standard static synthesis environments and includes an RTL description of the design to be synthesized and a set of timing and physical constraints. The unate step includes reading the design and initializing, simplifying the logic, marking inversions, marking binate cones for duplication, identifying endpoints, performing a reverse traversal, an optional phase optimization, committing netlist changes, primary inputs processing, primary outputs processing, and a final check and save.

Abstract: A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includes a plurality of transmitter cells consisting of a driver cell and digital to analog converter connected to driver cell. A hybrid circuit connects between the transmitter outputs and receiver inputs for separating a receiver signal from the transmitter signal responsive to a tuning signal.

Abstract: A battery protection structure is described. The structure provides battery overcharging protection while allowing for minimal battery voltage drop during normal battery operation. One resistance element sets voltage drop during normal operation, and the sum of two resistance elements sets the maximum battery charging current which will be allowed. The structure provides protection against single component failures.

Abstract: A large diameter glass wafer is pattern-etched to provide a plurality of elongated lens elements arranged side-by-side, the etching leaving small rods in place to keep the lens elements connected to the wafer during mirror processing. The etching provides curved surfaces for lenses and flat surfaces for mirrors. The mirrors are formed by selectively depositing reflective material on the flat surfaces. The reflective material may comprise an oxide, nitride, sulfide, or fluoride of a transition metal. The flat surfaces that define the mirrors are disposed at angles to the longitudinal dimension of each lens element. In use in an optical disc system, light from a laser diode is reflected by the mirrors and directed at an optical disc through a first lens. Light returns from the disc on a parallel path through a second lens, passes through the lens element, and is directed at a photodetector. The system may include an elongated base element attached to each lens element.

Abstract: A fluorescent lamp assembly includes a fluorescent lamp ballast capable of detecting at least one of a plurality of input signals and generating an output signal. The output signal is associated with a power level that is based on the at least one detected input signal. The fluorescent lamp assembly also includes a fluorescent lamp capable of receiving the output signal and generating light. An intensity of the light is based on the power level associated with the output signal.

Abstract: A hierarchical WRAN includes a relay station (RS) possessing dual roles. A RS acts from the perspective of a base station (BS) as a consumer premise equipment (CPE) terminal just as any other first tier CPE terminal. Simultaneously, the RS, from the perspective of other second tier CPEs, acts as a BS providing all of the functional capabilities of a BS. The RS includes dual medium access control (MAC) functions in which a first MAC function serves to interface the RS with the BS while the second MAC function serves to interface the RS with the at least one CPE terminal. The RS further includes a convergence layer that maps, at the RS, the first MAC to the second MAC. The dual MAC capability of the RS enables the RS to pipeline frame transmission in both single and multi-channel operations.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.