Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.

Abstract: A radiometer sensor includes a target plate and a micro-mechanical spring which supports the target plate above a base support. This construction allows for displacement of the target plate in a direction perpendicular to the base support in response to radiation which is received by a top surface of the target plate. The sensor is enclosed within a housing that defines a sealed interior chamber within which a vacuum has been drawn. The target plate preferably is non-deformable in response to received radiation. Capacitive or piezoelectric sensors are provided to detect the displacement of the target plate, and the measured displacement is correlated to determine a received radiation level. Radiometer sensor output signals are quantized and signal processed so as to make a radiation level determination.

Abstract: A method for synthesizing a domino logic circuit design from a source circuit definition using a static logic circuit synthesis tool includes generating a preliminary domino logic circuit design using the circuit synthesis tool and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design.

Abstract: An apparatus for a Universal Serial Bus (USB) and wireless smart card is provided. The apparatus includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. Furthermore, an apparatus for a triple-mode smart card is also provided herein. The apparatus for the triple mode smart card includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. The apparatus for the triple mode smart card operates in one of a wireless mode, a USB mode and an International Standards Organization 7816 mode or other wired mode. Furthermore, the apparatus for any of these smart cards could operate in both the wireless and wired mode(s) without conflict, and without switching power off and on to change configuration.

Abstract: A differential amplifier receives a differential input signal and generates an output signal at an output node. An auxiliary circuit coupled to the differential amplifier operates to improve slew rate response. In quiescent and small signal situations with respect to the differential input signal, the auxiliary circuit does not alter or change operation of the differential amplifier. However, in situations where a large signal change is experienced with respect to the differential input signal, the auxiliary circuit functions to speed up the sourcing and sinking current to/from the output node. A stability compensation capacitor coupled to the output node is accordingly more quickly charged or discharged and an improvement in slew rate performance of the differential amplifier is experienced.

Abstract: A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area, power consumption, and cost. The use of static buffers simplifies the clock network and clock tree synthesis. A domino logic circuit including at least one logic gate including a fast input and a slow input, and a static buffer inserted in series with the fast input of the logic gate. The falling time of the static buffer is set to be greater than a defined minimum falling time and less than a defined maximum falling time.

Abstract: A method of fabricating an integrated circuit sensor package. The method comprises the steps of: 1) mounting a substrate on a first mold block, the substrate comprising a substantially planar material having a first substrate surface and a second substrate surface that contacts a mounting surface of the first mold block; 2) placing an adhesive on the first substrate surface; 3) placing an integrated circuit sensor on the adhesive; and 4) pressing a second mold block against the first substrate surface. The second mold block comprising a cavity portion for receiving the integrated circuit sensor, a contact surface surrounding the cavity portion, and a compliant layer mounted with the cavity portion. Pressing the second mold block against the first substrate surface causes the contact surface to form with the first substrate surface a seal surrounding the integrated circuit sensor.

Abstract: A device and method that determine a freewheeling rotation of an electric motor. The method includes steps of measuring first and second signals from respective first and second windings of an unenergized motor, and determining from the first and second signals whether the unenergized motor is rotating. The method may also include determining from the first and second signals the direction of rotation if the unenergized motor is rotating. The method may further include measuring a third signal from a third winding of the unenergized motor, and determining whether the motor is rotating may include determining that the motor is not rotating if the first, second, and third signals are equal. The first and second signals may each include a respective back voltage.

Abstract: An apparatus is provided that includes a light source, an array of light-reflecting devices, and a processor for positioning the light-reflecting devices so as to display an image on the display screen. Each of the light-reflecting devices selectively reflects the light from the light source onto a corresponding pixel of a display screen. The processor positions a first of the light-reflecting devices such that light from the light source is reflected by the first light-reflecting device onto a first pixel of the display screen, which is different than the pixel of the display screen that corresponds to the first light-reflecting device.

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address(es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract: An apparatus for a Universal Serial Bus (USB) and wireless smart card is provided. The apparatus includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. Furthermore, an apparatus for a triple-mode smart card is also provided herein. The apparatus for the triple mode smart card includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. The apparatus for the triple mode smart card operates in one of a wireless mode, a USB mode and an International Standards Organization 7816 mode or other wired mode. Furthermore, the apparatus for any of these smart cards could operate in both the wireless and wired mode(s) without conflict, and without switching power off and on to change configuration.

Abstract: A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on the NMOS side, for stack etch, channel-stop implant, and silicon recess etch (optional); the other masking step is exactly complementary, and performs the analogous operations on the PMOS side. After these two steps are performed (in either order), an additional nitride layer can optionally be deposited and etched to cover the sidewall of the active stack. Field oxide is then formed, and processing then proceeds in conventional fashion.

Abstract: A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as for example a high-ohmic poly resistor. The method transfers a pattern defined by a mask onto the screening layer by selectively removing portions of the screening layer in accordance with the pattern. Portions of the auxiliary layer that are not protected by the screening layer are removed using a plasma gas selective to the auxiliary layer material, without removing the area of the auxiliary layer that overlays the portion of the circuit component, thereby protecting the circuit component from the plasma gas via the screening layer and auxiliary layer.

Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.

Abstract: A domino clocking method includes providing a domino logic circuit including first and second coupled domino gates, providing a first clock signal for clocking the first domino gate, and providing a second clock signal for clocking the second domino gate, wherein the first clock signal has a shortened positive phase duty cycle relative to the second clock signal. The positive phase of the first clock signal is shortened by an amount greater than or equal to a precharge time plus a falling edge skew between the clock signals. The footer transistor in the second domino gate can be eliminated. The first and second clock signals have the same frequency. The timing of the data presented to the first domino gate, and the first and second clock signals is adjusted so that there is no direct path between the power supply voltage and ground during the entire precharge phase of the second domino gate.

Abstract: A system controls an induction motor driven by a power inverter circuit. An operational amplifier circuit is operatively connected to the power inverter circuit and operative therewith for sensing DC current and controlling acceleration and deceleration of the induction motor. The operational amplifier circuit includes a first operational amplifier operative in a motoring mode to have a positive polarity output and remain substantially at zero during a regeneration mode. A second operational amplifier circuit is operative in a regeneration mode to have a negative polarity output and remain substantially at zero in a motoring mode.

Abstract: A method and apparatus for comparing a stored data word to a comparison data word in a magnitude content addressable memory (MCAM). The magnitude comparator receives the data value and a comparison value as inputs, and produces two magnitude signals as outputs. The first magnitude signal indicates whether the comparison value is greater than the data value and the second magnitude signal indicates whether the comparison value is less than the data value. The magnitude comparator also receives magnitude signals from the preceding MCAM cell. The previous magnitude signals are output as the first and second magnitude signals when the data value and the comparison value are equal. The MCAM enables data words of arbitrary length to be compared with comparison words.

Abstract: A static frequency divider circuit includes a first and second latch that are interconnected by a series path circuit and by a feedback path circuit. Each of the latches includes a reading BALLSACKbranch and a latching branch. The series path circuit includes a push-pull current driver to speed state transitions between the latching branch of the first latch and the reading branch of the second latch. Similarly, feedback path circuit includes a push-pull current driver to speed state transitions between the latching branch of the second latch and the reading branch of the first latch.

Abstract: An integrated data jitter generator for the testing of high speed serial interfaces is provided. A transmit timing generator for use in a transmit data path includes a high frequency clock generator such as a phase-locked loop or a delay-locked loop having an input for receiving an oscillator or reference clock input. A clock modulator receives both an existing low frequency modulation signal and a high frequency modulation signal. A high-speed modulated clock signal is generated to enable jitter testing by a downstream-coupled receiver. Fixed frequencies such as 3, 6, 125, 150, 250, 300, 750, or 1500 MHz are used for the high-speed modulation signal, but any high-speed modulation frequency can be used to generate the desired amount of jitter. Likewise, the amplitude of the high frequency modulation signal can also be varied as desired.

Abstract: A parity generation circuit includes a plurality of bit-generation circuits. Each bit-generation circuit receives respective data bits and a respective hard latch signal, and operates to generate a parity signal indicating the parity of the corresponding data bits when the hard latch signal is inactive. Each bit-generation circuit drives the parity signal to a set value when the hard latch signal is active. An output circuit is coupled to the bit-generation circuits to receive the parity signals and operates to generate an output parity signal in response to the parity signals from the bit-generation circuits.