Abstract: A method for generating a temperature-compensated control signal is provided. The method includes receiving a constant control signal. A temperature-compensated control signal is generated based on the constant control signal. The temperature-compensated control signal is provided to a variable gain amplifier. The temperature-compensated control signal is operable to cause the variable gain amplifier to function independently of temperature.

Abstract: A method for varying gain exponentially with respect to a control signal is provided. The method includes receiving a primary control signal. A secondary control signal is generated based on the primary control signal. The secondary control signal is provided to a variable gain amplifier and is operable to exponentially vary a gain for the variable gain amplifier with respect to the primary control signal.

Abstract: Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key including a first ciphering branch arranged to encrypt the at least part of the input data; a second ciphering branch arranged to generate the tag; and a single key schedule unit arranged to receive the key, to generate at least one sub-key based on the key and to provide the at least one sub-key to the first and second ciphering branches.

Abstract: An integrated heater formed as a field effect transistor in a semiconductor substrate, with the transistor having source and drain regions with a channel region extending therebetween to conduct current. The channel region has a resistance when conducting current to generate heat above a selected threshold. A dielectric layer is disposed on the channel region and a gate electrode is disposed on the dielectric layer to control the current of the channel region. A thermally insulating barrier is formed in the semiconductor material and may extend about the transistor. The object to be heated is positioned to receive the heat generated by the resistance of the channel region; the object may be a fluid chamber.

Abstract: Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key, the algorithm including iterative computations by at least two operation units, the circuitry including a pipeline including an input selection unit arranged to receive first data values to generate encryption sequences with the ciphering algorithm, second data values to generate temporary tags with the ciphering algorithm and an output of the pipeline; a first stage arranged to receive an output of the input selection unit and including at least a first operation unit; and a second stage arranged to receive an output of the first stage, including at least a second operation unit and providing the output of the pipeline.

Abstract: A system and method for configuring and managing the connectivity of a broadband, cable modem network station to a network, including a state-driven network manager having a centralized error handling state and peripheral states for initialization, dynamic host configuration, configuration download, start simple-network-management, and an operational state. The operational state monitors for error and other messages communicated from other states and sends error messages to the centralized error-handling state and request messages to an operational support system interface management task. The error handling state receives error messages and requests error event logging from the operational support system interface management task. A change upstream-or-downstream channel task optimizes channel selection.

Abstract: An integrated circuit die having an active area that must remain exposed after packaging is secured by a compliant die attachment by which the integrated circuit die is held in position within a transfer mold during encapsulation. The compliant die attachment may comprise a flexible, compressible tape having pressure-sensitive adhesive, alone or with a rigid substrate support, or a compliant adhesive preferably applied only around a periphery of the die attach area. Deformation of the compliant die attachment under mold clamping pressure allows complete contact of the mold with the active area, preventing bleeding of the encapsulating material under the edge of a mold portion onto the active area.

Abstract: A microfabricated structure and method of making that includes forming a first layer of material on a substrate, forming patterned sacrificial material having a predetermined shape on the first layer of material, and forming a second layer of material over the first layer and the patterned sacrificial material, which is then removed to form an encapsulated cavity. Ideally, the first and second layers are formed of the same type material. A structural support layer can be added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

Abstract: A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.

Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines, the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store information within the element in any one of at least three logic states.

Abstract: The contact opening through an insulating layer is formed having a straight sidewall portion and a bowl shaped sidewall portion. The bowl shaped sidewall portion is near the top of the insulation layer to provide an enlarged diameter of the contact opening at the top relative to the bottom. A conductive material is then formed in the contact opening in electrical contact with a lower conductive layer. The conductive material forms a plug having an enlarged head, such as a nail head or a flat heat screw shape. The enlarged head protects the silicon and a barrier layer, if present, within the contact from being etched by any subsequent anisotropic etches. Thus, when an electrical interconnection layer such as aluminum is formed overlying the contact plug, the plug acts as an etch stop to prevent etching of a barrier layer of the barrier layer within the contact opening.

Abstract: A prior art direct back EMF detection method synchronously sampled motor back EMF during PWM “off” time without the need to sense or re-construct the motor neutral in a sensorless brushless DC (BLDC) motor drive system. Since this direct back EMF sensing scheme requires a minimum PWM “off” time to sample the back EMF signal, the duty cycle cannot reach 100%. Also in some applications, for example, high inductance motors, the long settling time of a parasitic resonant between the motor inductance and the parasitic capacitance of power devices can cause false zero crossing detection of back EMF. An improved direct back EMF detection scheme samples the motor back EMF synchronously during PWM “on” time at high speed. In the final system the motor back EMF can be detected during PWM “off” time at low speed, and it is detected during PWM “on” time at high speed.

Abstract: A method for providing cascaded trie-based network packet search engines is provided. A search command is received at one of the network packet search engines. The search command comprises a specific search key. A determination of a longest prefix match based on the specific search key is made at the network packet search engine. A determination is made at the network packet search engine regarding whether the longest prefix match comprises an overall longest prefix match among the cascaded network packet search engines such that any of the cascaded network packet search engines may comprise the overall longest matching prefix independently of position relative to the other cascaded network packet search engines.

Abstract: There is disclosed an apparatus for implementing special mode playback operations in a digital video recorder. The apparatus comprises an Intra frame indexing device capable of receiving an incoming MPEG video stream and identifying therein data packets associated with Intra frames, wherein the Intra frame indexing device modifies header information in a first data packet associated with a first Intra frame to include location information identifying a storage address of a second data packet associated with a second Intra frame.

Abstract: A method includes receiving first encoded data associated with one or more first lanes and decoding the first encoded data to produce decoded data. The method also includes encoding the decoded data to produce second encoded data associated with one or more second lanes and transmitting the second encoded data. In some embodiments, the method may further include multiplexing a plurality of code group sequences (the second encoded data) into the one or more second lanes, and the number of first lanes may be greater than the number of second lanes. In other embodiments, the method may also include demultiplexing a plurality of code group sequences from the one or more first lanes into a plurality of the second lanes, and the number of first lanes may be less than the number of second lanes.

Abstract: A device, such as an integrated circuit or an electronic circuit component is affixed to a substrate. A first encapsulation structure encases a first integrated circuit and has at least one groove formed therein. An adhesive partially fills the groove in the first encapsulation structure. A second integrated circuit is affixed to the first encapsulation structure by use of the adhesive in the groove. A second encapsulation structure at least partially encases the first encapsulation structure, the first integrated circuit, and the second integrated circuit.

Abstract: A battery monitor circuit. The circuit includes a control module, a resistive load having a resistive value between a first and a second terminals and a part of that resistive value between the first and an intermediate terminals, a switch configured to couple the full load between circuit input and a common potential in response a pulse signal, a first comparator having inputs separately coupled to a voltage reference and the intermediate terminal, a second comparator having inputs separately coupled to the voltage reference and an input potential, a latch, a detection module having input coupled to second comparator output, and an alarm module. The latch is configured to latch a value at output of first comparator to another input of the detection module in response to the pulse signal; if input potential is less than a preselected magnitude, detection module output is configured to activate the alarm module.

Abstract: A one-time programmable circuit uses forced BJT hFE degradation to permanently store digital information as a logic zero or logic one state. The forced degradation is accomplished by applying a voltage or current to the BJT for a specific time to the reversed biased base-emitter junction, allowing a significant degradation of the junction without destroying it.

Abstract: A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of the code in the ROM; 2) a lockable cache; 3) core processor logic operable to read from an associated memory a patch table containing a first table entry, the first table entry containing 1) the first new instruction and 2) a first patch address identifying a first patched ROM address of the at least a portion of the code in the ROM. The core processor logic loads the first new instruction from the patch table into the patch buffer, stores the first replacement cache line from the patch buffer into the lockable cache, and locks the first replacement cache line into the lockable cache.

Abstract: A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.