Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

Abstract: An E2PR4 Viterbi detector includes a recovery circuit and receives a signal that represents a sequence of values, the sequence having a potential state. The recovery circuit recovers the sequence from the signal by identifying a surviving path to the potential state and, after identifying the surviving path, adding a modified branch metric to the path metric of the surviving path to generate an updated path metric for the potential state. Updating the path metric of the surviving path after the surviving path is selected allows the E2PR4 Viterbi detector to be smaller and/or faster than an E2PR4 Viterbi detector that updates the path metric before selecting the surviving path.

Abstract: A method for creating and maintaining semi-dynamic frequency hopping communities. Each community is a set of neighboring cells, such as wireless regional area networks (WRANs) according to IEEE 802.22, that follow a protocol defining coordinated frequency hopping operations, e.g., hopping is performed by community members according to a leader-defined hopping pattern rather than to channels selected in the prior operation period. Each community has one leader base station and one or more community member base stations. The leader determines membership, calculates hopping patterns for all members, and distributes the hopping information to the community members. Members provide their neighborhood and channel availability information, e.g., information about their sensing results and channel usage of neighboring WRANs.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: A method includes extracting at least one object file from a library of object files. The method also includes identifying an interprocedural optimization associated with a plurality of object files. The plurality of object files includes the at least one extracted object file. The method further includes invoking recompilation of at least one of the plurality of object files to implement the identified interprocedural optimization. In addition, the method includes generating at least one executable file using the at least one recompiled object file. The plurality of object files could include interprocedural summary information generated by a compiler during a compilation of at least one source file and a compiler internal representation associated with the compiler during the compilation. The interprocedural optimization could be identified using the interprocedural summary information, and the at least one recompiled object file could be generated using the compiler internal representation.

Abstract: A power-on reset circuit. The power-on reset circuit includes a switch, a current source coupled between a first potential and a switch first contact; a resistive device having a resistive-device first contact coupled to the first potential; a first module coupled between a second potential and a switch second contact; a second module coupled between the second potential and resistive-device second contact; and an inverter having an inverter input coupled to the resistive-device second contact. Current through the second module mirrors current through the first module. If a first mirrored potential of the second potential present on a switch control contact is greater than a preselected value, the switch first contact is coupled to the switch second contact. Otherwise, the switch first contact is decoupled from the switch second contact.

Abstract: A USB mass storage device includes a memory, USB interface and USB controller. A biometric circuit provides biometric authentication and a secure microcontroller is operatively connected to the biometric circuit and the USB controller and operative in accordance as a trusted platform and having a command set to access security functions and trust authentication of a user using the biometric circuit.

Abstract: A threshold personalization circuit for a reset or supervisor chip includes personalization fuses, which shift a resistor divider to provide a variety of selectable voltage thresholds. The personalization fuses may provide hundreds of millivolts of adjustment. The threshold personalization circuit further includes trim fuses to fine tune the threshold to within a few millivolts of the target threshold voltage. The threshold personalization circuit includes a test mode to cycle through to a particular personalization trim, such that at prelaser testing the personalized value is found (the fuse blow for personalization is emulated) and then the trim fuse amount can be based on the actual final personalized voltage. This results in very accurate threshold voltages for all personalized values.

Abstract: An output driver for an integrated circuit that asserts at very low power supply voltages includes a first input voltage node, a first power supply voltage node, an output voltage node, a first internal circuit node, a first resistive element coupled between the first power supply voltage node and the first internal node, a first transistor having a gate coupled to first input voltage node, a drain coupled to the first power supply voltage node, and a source coupled to ground, a second transistor having a gate coupled to the first internal circuit node, a drain coupled to the output voltage node, and a source coupled to ground, and a third transistor having a gate coupled to the first internal circuit node, a drain coupled to the output voltage node, and a source coupled to ground, wherein the first and second transistors have a first Vt threshold voltage, and the third transistor has a second Vt threshold voltage lower than the first threshold voltage.

Abstract: A hybrid ionized physical vapor deposition technique to form liner films for vias, trenches, and other structures of integrated circuits. The techniques involves depositing liner materials within a via, hole, trench, or other structure in a neutral state, using, for example, physical vapor deposition. The liner materials deposited in this step have an ionization ratio of less than ten percent, and no bias potential is applied to an underlying substrate. The technique also involves depositing liner materials in ionized form in the same via using ionized physical vapor deposition. The liner materials deposited in this step have an ionization ratio far more than ten percent, and an optional bias potential may be applied to the underlying substrate. After liner film is formed, any other suitable actions or processing steps may take place including building additional metallization and dielectric layers and vias or trenches to produce a multi-level interconnect system.

Abstract: A method includes generating an encoded data block, dividing the encoded data block into a plurality of sub-blocks, and transmitting the plurality of sub-blocks over a plurality of physical medium attachments. The encoded data block may be generated using 64B/66B encoding, and the data being encoded could first be decoded using 8B/10B decoding. Another method includes receiving a plurality of sub-blocks over a plurality of physical medium attachments, generating an encoded data block using the plurality of sub-blocks, and recovering data encoded in the encoded data block. The data may be recovered from the encoded data block using 64B/66B decoding, and the recovered data may be subsequently encoded using 8B/10B encoding. Each physical medium attachment may be capable of serializing data for transmission over a physical transmission medium (such as printed circuit board tracks or lanes) and deserializing data received over the physical transmission medium.

Abstract: A system of detecting biometric and non-biometric, standard smart card devices includes a smart card host and smart card device reader, which is operable for receiving an Answer to Reset signal and determining whether the smart card device comprises a biometric or non-biometric, standard smart card device. If a biometric smart card device is detected, the smart card reader is operable for applying power used for standard smart card device operation to a first contact and applying power used by a biometric circuit to a second contact, and if a non-biometric, standard smart card device is detected, applying power only to the first contact.

Abstract: A reset circuit includes a power supply supplying a power supply voltage, and a band-gap reference that generates a voltage reference signal. A resistor start-up circuit is responsive to the voltage reference signal, and further responsive to an increase in the power supply voltage. The resistor start-up circuit generates a first current when the power supply voltage increases to a first predetermined voltage, and further generates a second current when the power supply voltage increases to a second predetermined voltage. When the second current generated by the resistor start-up circuit is supplied to a resistor divider, the resistor diver delivers an output voltage that is a predetermined portion of the power supply voltage. A comparator compares the voltage reference signal with the resistor divider output voltage, and generates a reset signal when the resistor divider output voltage equals the voltage reference signal.

Abstract: A method for manufacturing an electronic tag to be affixed onto a product includes providing, in an electrically conductive film of a foil for packaging, packing or transporting the product, areas devoid of any electrically conductive material for delimiting in the electrically conductive film at least one antenna pattern for forming an antenna for an RFID tag. A semiconductor chip is connected to the antenna for forming an electronic tag.

Abstract: An apparatus includes a display panel capable of displaying content. The apparatus also includes a light sensor having an integrated circuit and a photo-sensitive device. The photo-sensitive device is capable of measuring an amount of ambient light. The integrated circuit is capable of performing one or more functions associated with the display of the content on the display panel. The apparatus further includes a controller capable of adjusting one or more characteristics of the display panel based on the amount of ambient light measured by the light sensor. The integrated circuit and the photo-sensitive device may be formed on one side of a semiconductor wafer, and the photo-sensitive device may be exposed to the ambient light through an opening in an opposing side of the semiconductor wafer.

Abstract: A preamplifier for correcting for thermal asperity transients in disk drives using magneto resistive read heads. The preamplifier has an input gain stage receiving a signal from the read head and an output buffer outputting a reader output to a read channel that is filtered of thermal asperity transients by a high pass filter positioned between the input gain stage and the output buffer. The high pass filter is voltage controlled based on an input control signal from a filter controller. The filter controller uses a low pass filter functioning as a peak detector to detect peaks in either the input or output voltage of the high pass filter. The low pass filter output is applied to a non-linear function generator generating the control signal for the high pass filter based on an increasing function of the absolute value of the low pass filter output.

Abstract: A compound camera system comprising component cameras that generate image data of an object and a processor that receives first image data from a first component camera and second image data from a second component camera and generates a virtual image. The processor projects virtual pixel data (u,v) to generate point data (x,y,z) located at depth, z=Z1, of a object plane of the object and projects the said point data (x,y,z) to generate first pixel data (u1,v1) located at a image plane of the first image. The processor also projects said point data (x,y,z) located at the depth, z=Z1, of the said object plane to generate second pixel data (u2,v2) located at the second image.

Abstract: Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source or destination operand is true, where the predicate bit of the destination register is set to the logical AND of the source registers' predicatest for most instructions. Similarly, in a non-programmable processor synthesized with predicated operand support, an operator will perform the associated function depending on the state of inputs' predicates and the output predicate, which is normally evaluated as the logical AND of the inputs' predicates.

Abstract: A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond pad that covers and fills the substrate cavity. The wire bond pad also has portions that form a wire bond cavity for receiving the ball bond. The ball is wirebonded to the sides and bottom of the wire bond cavity. The sides of the wire bond cavity provide additional strength to the bond to resist shear and tensile forces that may act on the wire.

Abstract: A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the substrate. The thin film power transistor further includes a dielectric layer, at least a portion of which is disposed between (i) the gate and (ii) the first and second doped regions. In addition, the thin film power transistor includes a plurality of contacts contacting the plurality of first doped regions, where the plurality of first doped regions forms a source and a drain of the thin film power transistor. The first doped regions could represent n-type regions (such as N? regions), and the second doped region could represent a p-type region (such as a P? region). The first doped regions could also represent p-type regions, and the second doped region could represent an n-type region.