Abstract: A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.

Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

Abstract: A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.

Abstract: A device for managing operation of an object capable of contactless communication with a reader magnetically coupled to the object includes a modulator configured to modulate an impedance of a load connected across terminals of an antenna of the object during a transmission phase during which information is transmitted from the object to the reader. The device further includes a monitor configured to carry out a monitoring phase, prior to the transmission phase. The monitoring phase includes a test modulation of the impedance of the load, a monitoring of a level of amplitude modulation of a modulated test signal present at the antenna of the object and resulting from the test modulation, and a capacitive modification of the impedance of the load if this level is lower than a threshold.

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

Abstract: An embedded system includes a peripheral and system-on-a-chip executing virtual machines and a hypervisor. The peripheral includes a crossbar circuit receiving digital sensor signals and selectively outputting the digital sensor signals to different outputs, queue circuits each receiving a different one of the digital sensor signals from the crossbar circuit, and queue protection circuits associated with the queue circuits and selectively permitting access to one of the queue circuits by the virtual machines. The hypervisor controls the queue protection circuits to set which of the virtual machines may access which queue circuits. A sensor protection circuit selectively permits reading of the digital sensor signals from the crossbar circuit by the queue circuits. The hypervisor controls the sensor protection circuit to set which of the queue circuits may access each of the digital sensor signals from the crossbar circuit.

Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.

Abstract: In accordance with embodiments, methods for the recovery of security credentials of a Bluetooth mesh network are disclosed. A computing device of the Bluetooth mesh network receives user login information, and generates a network key of the Bluetooth mesh network based on the user login information. The computing device generates an application key of a first node to be provisioned based on user login information. A device key is generated using the unicast address of the first node and part of user credentials. The current sequence number is recovered by one of the four techniques depending on the characteristics of the network. The unicast addresses of the nodes are assumed to be sequential and later validated by sending messages. IV index is recovered using processes defined in the Bluetooth mesh standard. After recovery of the above parameters, the mesh network can operate normally using the aforementioned computing device.

Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.

Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.

Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.

Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

Abstract: A PLL includes a phase-frequency-detector-and-charge-pump-circuit (PFDCPC) receiving a reference signal and divided signal, and generating a charge-pump current. A loop-filter is between output of the PFDCPC and a reference-voltage. A first voltage-to-current converter (V2I1) has low gain, and a second voltage-to-current converter (V2I2) has high gain. A low-gain-path is between outputs of the PFDCPC and V2I1, and a high-gain-path is between the outputs of the PFDCPC and V2I2. A current-controlled-oscillator receives an input signal, and generates an output signal. A loop divider divides the output signal by a divider-value, producing the divided signal. The low-gain-path runs directly from the PFDCPC, through the V2I1, to the input of the current-controlled-oscillator. The high-gain-path runs from the PFDCPC to the loop-filter, from a tap of the loop-filter to a low-pass filter through a current mirror, from a tap of the low-pass filter through the V2I2, to the input of the current-controlled-oscillator.

Abstract: A temperature sensing circuit a switched capacitor circuit selectively samples ?Vbe and Vbe voltages and provides the sampled voltages to inputs of an integrator. A quantization circuit quantizes outputs of the integrator to produce a bitstream. When a most recent bit of the bitstream is a logic zero, operation includes sampling and integration of ?Vbe a first given number of times to produce a voltage proportional to absolute temperature. When the most recent bit of the bitstream is a logic one, operation includes cause sampling and integration of Vbe a second given number of times to produce a voltage complementary to absolute temperature. A low pass filter and decimator filters and decimates the bitstream produced by the quantization circuit to produce a signal indicative of a temperature of a chip into which the temperature sensing circuit is placed.

Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

Abstract: A method includes receiving a plurality of digital feedback signals from a voltage converter, controlling the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, the voltage converter receiving input from a DC voltage bus and providing output to drive a lighting load, and receiving a plurality of feedback signals from a power factor correction circuit that receives a rectified mains voltage and provides output to the DC voltage bus, and based thereupon operating the power factor correction circuit in transition mode or discontinuous mode based upon the user desired brightness level and a threshold brightness. The plurality of feedback signals include an input sense signal that is a function of the rectified mains voltage as drawn by the power factor correction circuit and an output sense signal that is a function of the output provided to the DC voltage bus.

Abstract: A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.