Abstract: A load is powered between positive and negative rails. A switching converter generates the negative rail voltage based on an input voltage, with a power transistor involved therein. A replica generator produces a replica voltage mirroring the drain-to-source voltage of the power transistor. A buffer buffers the replica voltage. A first switch selectively connects the buffered voltage to an output node, in response to a control signal with a duty-cycle proportional to the input voltage divided by the negative rail voltage. A second switch selectively connects the buffered voltage to ground, according to the inverse of the control signal, resulting in a PWM signal at the output node. An output filter filters the PWM signal to generate a sense voltage indicative of the output current flowing from the load device. A processing circuit determines the input current from the positive rail to the load device based on the sense voltage.

Abstract: A process forms a high electron mobility transistor (HEMT) device with a recessed gate without damaging sensitive areas of the HEMT device. The process utilizes a first epitaxial growth process to grow a first set of layers of the HEMT. The epitaxial growth process is then stopped and a passivation layer is formed on the first set of layers. The passivation layer is then patterned to provide a passivation structure at a desired location of the recessed gate electrode. The channel layer and one or more barrier layers are then formed in a second epitaxial growth process in the presence of the passivation structure. The result is that the channel layer and the barrier layer growth around the passivation structure. The passivation structure is then removed, effectively leaving a recess in the channel layer. The gate electrode is then formed in the recess.

Abstract: An ESD protection device includes at least one semiconductor electronic switch electrically coupled in parallel with a diode. The semiconductor electronic switch and the diode each include at least one finger extending substantially parallel to a first direction. The fingers of the semiconductor electronic switch and of the diode are aligned with each other along this first direction.

Abstract: Sensor device with a microcontroller unit and a sensor including a transducer, which is coupleable to a device and generates a signal indicative of a physical quantity, and a processing circuit including: a conversion stage which generates samples of the physical quantity; a data generation stage which generates data vectors as a function of the samples, each data vector being formed by programmable quantity values; and a decision stage. The microcontroller unit programs the decision stage so that it classifies the data vectors by executing a decision tree having a structure and thresholds.

Abstract: A time-of-flight (TOF) sensor includes a timing generator generating a timing reference, a first array of TOF-related components including rows of TOF-related components, with each row receiving the timing reference, and a dummy row of TOF-related components. The TOF sensor also includes a second array of TOF-related components including rows of TOF-related components, with each row receiving the timing reference, and a dummy row of TOF-related components. A first path delivers the timing reference to the rows of the first array, the first path passing from the timing generator, through the dummy row of TOF-related components in the second array, to the first array of TOF-related components. A second path delivers the timing reference to the rows of the second array, the second path passing from the timing generator, through the dummy row of TOF-related components in the first array, to the second array of TOF-related components.

Abstract: An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

Abstract: The present disclosure relates to an image sensor comprising an array of pixels arranged in first rows and in first columns. The pixels are arranged in groups of N*N pixels, with N an integer equal to or higher than 2. In each group, the pixels of the group are distributed into one or more sub-groups of a plurality of pixels. Each pixel comprises: a photosensitive element, a first node coupled to the photosensitive element, a second node common to all pixels of a same sub-group, and coupled to a first potential, a first transistor coupling the first and second nodes to each other, a second source-follower transistor having a gate connected to the first node, and a third transistor coupling the source of the third transistor to a reading line.

Abstract: A device includes a first MOS transistor connected between first and second nodes, a selectively activatable current source connected between the second node and a third node and a circuit configured to control the first transistor to regulate a voltage at the second node to a first set point value. The device further includes a second MOS transistor connected between the first node and a fourth node, and having its gate connected to the gate of the first MOS transistor, a third MOS transistor connected between the third and fourth nodes, a switch connected between the second and fourth nodes, and another circuit configured to control the third transistor to regulate a voltage at the fourth node to a second set point value.

Abstract: The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.

Abstract: A test-circuit includes a PLL-divider outputting first and third clock-signals as PLL clock-signals during functional mode and a capture-phase of transition and stuck-at-modes, and outputting a second clock-signal based upon an external clock-signal as an ATE clock-signal during a shift-phase of the transition and stuck-at-mode. An OCC passes the clock-signals in functional mode, transition capture mode, and stuck-at capture mode through sub-paths within first paths within first and second clock selection circuits so the first and third clock-signals are passed through less than the entire first paths, the sub-paths being first and second functional clock paths.

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

Abstract: Disclosed herein is a method of operating a static random access memory (SRAM) device in retention mode. The method includes powering an array of SRAM cells between first and second voltages in retention mode, detecting process variation information about the array of SRAM cells, and generating a control word based thereupon. The method continues with generating a reference voltage that is proportional to absolute temperature and having a magnitude curve that is set by the control word, and then maintaining the second voltage as being equal to the reference voltage.

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Abstract: A debug method implemented by a first near field communication (NFC) device includes a step of storing, in a memory of the first NFC device, one or more parameters which are associated with the operation of the first NFC device during a communication with a second distant NFC device. The first NFC device then uses an answer to select (ATS) communication, sent in response to receipt of an answer to select (ATS) communication, to send the stored one or more parameters to the second distant NFC device.

Abstract: A transistor suited for use as an RF switch includes a semiconductor layer and a stack of a gate insulator layer and a conductive gate layer. A length of the conductive gate layer is smaller on the side of a lower surface, located in the vicinity of the gate insulator layer, and is greater on the side of an upper surface, opposite to the lower surface. Lateral sides of the conductive gate layer are covered, on a lower portion, with a first material and, on an upper portion, with a second material. The first material has a Young's modulus greater than a Young's modulus of the second material.

Abstract: The present disclosure is directed to kickback detection for devices, such as handheld drills. Kickback is detected using a gyroscope and an accelerometer, and is detected at the end of each of a plurality of time windows. At the end of each time window, kickback is detected based on, for example, a variance of a norm of gyroscope measurements. False kickback detections are then removed based on, for example, a minimum and a mean of accelerometer measurements. Kickback detection is completed before the next time window begins.

Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.

Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.

Abstract: A circuit includes a first capacitance array formed by n nominally equal capacitive elements. A first electrode of each capacitive element is coupled, via respective switches to either a reference voltage or ground. A differential amplifier has a first input coupled to an output of a first capacitance array, a second input grounded, and an output generating a voltage ramp. A capacitive feedback circuit couples the output of the differential amplifier to the first input. A second capacitance array has an output coupled to the first input of the differential amplifier. The capacitive elements of the first capacitance array are organized in sets. The circuit operates by controllably coupling, set by set, second electrodes of the capacitive elements of the first capacitance array to the first input of the differential amplifier.

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.