Abstract: Semiconductor chips are arranged on a first surface of a common electrically conductive substrate having an opposite second surface. The substrate includes adjacent substrate portions having mutually facing sides with sacrificial connecting bars extending between adjacent mutually facing sides. A solderable metallic layer is present on the second surface extending over the sacrificial connecting bars. The solderable metallic layer is selectively removed (by laser ablation or etching, for example) from at least part of the length the sacrificial connecting bars. The common electrically conductive substrate is then cut along the length of the elongate sacrificial connecting bars to provide singulated individual semiconductor devices. Undesired formation of electrically conductive filaments or flakes bridging parts of the substrate intended to be mutually isolated is countered.

Abstract: An electronic device applies a frequency offset function to a first signal having a first frequency. The device includes a delay element configured to output a second signal corresponding to the first signal delayed by a duration equal to a first period of said signal divided by four. A circuit branch includes a first circuit configured to divide the frequency of the first signal by a given number coupled in series with a second circuit configured to implement an integration. The circuit branch outputs a third signal and a fourth signal. A single side band mixing circuit processes the first signal, second signal, third signal and fourth signal to generate an output signal.

Abstract: A device includes a substrate and an interconnection network on the substrate. The interconnection network includes at least a first level, at least a second level and a third level. The first level includes one or more capacitors. The third level includes a metallic shield. The second level is positioned between the first level and the substrate. The capacitors of the first level are entirely separated from the substrate by the shield. The second level is located between the first and third levels.

Abstract: An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.

Abstract: A method is for synchronizing power consumption data with trace data in a microcontroller debugging system. The method involves periodically sending synchronization requests from a host device to a synchronization manager within a debug probe. The synchronization manager retrieves the current power acquisition cycle number from a power acquisition circuit in response to each request, corresponding to a current sample of microcontroller power consumption. Each synchronization request, along with the retrieved cycle number, is sent to a protocol manager, which transmits the request to a microcontroller's debug-port. Upon receiving acknowledgment from the microcontroller, the protocol manager communicates these to the synchronization manager. The synchronization manager measures the latency between sending each synchronization request and receiving its acknowledgment, which is indicative of synchronization quality.

Abstract: The present disclosure is directed to an optical sensor package with light shielding material covering five sides. The optical sensor package includes a transparent layer, a substrate layer, sensor elements between the transparent layer and the substrate layer, a solder mask on the side of the substrate layer opposite the transparent layer, and layer of molding material covering five sides of the optical sensor package. The solder mask and layer of molding material prevent light from entering the sides of the optical sensor package or from traveling through the substrate layer and reflecting toward the sensor elements.

Abstract: A circuit is configured to perform an operation between a volatile memory and a cryptographic circuit in response to a write access request for writing one or more data values in the memory. The access request further includes a storage address in the memory. The operation includes steps for: writing the one or more data values; and for each of the one or more data values, generating a write access request, in the cryptographic circuit, for the data value, and generating a write access request, in the cryptographic circuit of the storage address. Additionally, a verification, in response to a read access request, from the processor, of a verification value is performed. The verification operation includes steps for: comparing the verification value with a reference value; and based on the comparing, authorizing access the volatile memory only for reading.

Abstract: The present disclosure relates to a regulator including a first transistor coupling an application node of a first power supply voltage to an output node of the regulator supplying a first regulated voltage; a feedback loop supplying a control signal to the first transistor and comprising a first charge pump circuit; a control signal generator of the first charge pump circuit; and a drop-down circuit between the control signal generator and the charge pump circuit.

Abstract: A power module includes an insulating body having a first main face and a second main face; a first contact plate and a second contact plate, respectively protruding through the first main face and through the second main face of the insulating body and accessible from the outside; a first power plate and a second power plate, at least partially embedded in the insulating body and facing each other. Power devices of a first group are accommodated on the first power plate and coupled to the first contact plate. Power devices of a second group are accommodated on the second power plate and coupled to the second contact plate. The first contact plate, the second contact plate, the first power plate and the second power plate, are stacked in a direction perpendicular to the first power plate and the second power plate.

Abstract: A method for manufacturing a MEMS device includes forming a first solid body by forming, on a substrate, a layered structure having a thickness of a value comprised between 4 and 10 ?m, with the layered structure having a first surface that is uniformly flat or planar throughout the extension thereof that faces the substrate. The method further includes forming, on a second surface of the layered structure opposite to the first surface in a direction, multiple transducer devices. The method then proceeds with coupling the first solid body to a supporting structure, and completely removing the substrate to expose said uniformly flat or planar surface.

Abstract: Laser direct structure (LDS) material is molded onto a semiconductor chip arranged on a substrate. The LDS material has a first thickness between a front surface of the LDS material and the substrate. A portion of the LDS material is removed (with a blade, for instance) to form a cavity having an end wall between the front surface of the LDS material and an electrically conductive formation on the substrate. At the cavity, the LDS material has a second thick ness smaller than the first thickness. Laser beam energy is applied to the LDS material at the end wall of the cavity to structure therein one or more vias that extend between the end wall of the cavity and the electrically conductive formation. The semiconductor chip and the electrically conductive formation are electrically coupled with electrically conductive material grown in the one or more vias laser structured in the LDS material.

Abstract: Various embodiments of wafers include a polycrystalline silicon carbide (SiC) layer or base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have grains with a grain size less than or equal to 1 millimeter (mm), and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage less than or equal to 75 ?m (micrometers). A monocrystalline silicon carbide (SiC) layer may be coupled to the polycrystalline silicon carbide (SiC) layer by a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.

Abstract: A polycrystalline silicon carbide (SiC) substrate with a density gradient between a first side of the polycrystalline SiC substrate and a second side of the polycrystalline SiC substrate opposite to the first side. A first density at the first side of the polycrystalline SiC substrate is less than a second density at the second side of the polycrystalline SiC substrate. The polycrystalline SiC substrate with the density gradient may be formed by forming a polycrystalline SiC base substrate with a sintering process followed by a post-sintering process. For example, the post sintering process may be at least one of the following of: applying a first temperature to the first side and a second temperature to the second side of the polycrystalline SiC substrate and performing a chemical vapor deposition (CVD) process to impregnate further silicon (Si) and carbon (C) atoms into the polycrystalline SiC base substrate.

Abstract: A method and apparatus for aligning electrical contact formations, such as bumps or solder balls, at a first surface of a Wafer Level Chip Scale Package (WLCSP) semiconductor device with electrically conductive pins in an array of electrically conductive pins such as “pogo” pins is provided. The semiconductor device includes, opposite the first surface, a second surface protected by a protection layer. The method includes aligning the semiconductor device to a first alignment member by exposing the protected second surface of the semiconductor device to a chamfered surface in the first alignment member. A second alignment member is aligned to the array of electrically conductive pins. The electrical contact formations are aligned with respect to the array of electrically conductive pins as desired in response to the first and second alignment members being mutually aligned, in response to the semiconductor device being “landed” onto the array of electrically conductive pins.

Abstract: At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.

Abstract: A memory cell comprising a stack of a conductive via, of a layer made of a phase-change material, and of a first electrode, the memory cell being covered with an encapsulation layer made of a silicon nitride having a density or volumic mass smaller than 2.2 g/cm3. A method of manufacturing a memory cell and a system having an integrated memory circuit that includes a plurality of memory cells is also provided.

Abstract: The present disclosure relates to an avalanche photodiode pixel including: a transistor adapted to be controlled by an enable signal having a first state for controlling the enabling of the pixel and a second state for controlling the disabling of the pixel, the transistor being configured to couple an avalanche photodiode of the pixel to a node of application of a substrate voltage when the enable signal is in the first state; and an output circuit adapted to be controlled by the enable signal and configured to provide a pixel output signal when the enable signal is in the first state and to block the pixel output signal when the enable signal is in the second state.

Abstract: A coupling and chaining bridge is configured to receive an original data value via a first bus coupled to one of a system bus of an electronic device and a first peripheral circuit of the electronic device. The original data value is transmitted by the coupling and chaining bridge to a second bus of the electronic device coupled to the other of the system bus and the first peripheral circuit. The coupling and chaining bridge is further configured to intercept the original data value and transmit a copy of the original data value to a third bus of the device that is coupled to a second peripheral circuit of the device.

Abstract: A “package-less” integrated circuit semiconductor device is produced by laminating first and second insulating films on opposed first and second surfaces of a semiconductor wafer having semiconductor dice integrated therein. Electrically conductive formations towards die pads of the semiconductor dice are provided in vias to the semiconductor wafer opened through the first insulating film laminated on the first surface of the semiconductor wafer. The semiconductor wafer provided with these electrically conductive formations is singulated at separation lines between neighboring semiconductor dice to produce individual semiconductor devices. Each device has: opposed first and second device surfaces having protective portions of the first and second insulating films laminated thereon, and side surfaces extending between the opposed first and second device surfaces, these side surfaces being left uncovered by the first and second insulating films.

Abstract: The present disclosure is directed to a device and method for human fall detection solution. Fall detection is performed by a low power inertial measurement unit (IMU) that is communicatively coupled between a pressure sensor and an application processor. The IMU includes one or more motions sensors, such as an accelerometer and gyroscope. The application processor is the main processor of the containing device. The IMU receives pressure sensor data from the pressure sensor, and executes the fall detection using both the pressure sensor data and accelerometer data.