Patents Assigned to STMicroelectronics (Research& Development)
  • Patent number: 12322684
    Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: June 3, 2025
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Pte Ltd
    Inventors: Roberto Tiziani, Laurent Herard
  • Patent number: 12324251
    Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: June 3, 2025
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Denis Rideau, Dominique Golanski, Alexandre Lopez, Gabriel Mugny
  • Patent number: 12323789
    Abstract: The present description discloses a secure element and a communication method, configured to implement at least one first application, and including a circuit configured to record routing data and a list and parameters of communication protocols compatible with the first application, verify the compatibility of a first communication protocol used by first messages intended for the first application with the protocols of the list, convert the first messages into second messages by using a second communication protocol in response to the first protocol not being compatible with at least one of the protocols of the list, and direct the second messages to the first application by using the routing data of the first application.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: June 3, 2025
    Assignees: STMicroelectronics (ROUSSET) SAS, STMicroelectronics Belgium
    Inventors: Olivier Van Nieuwenhuyze, Alexandre Charles
  • Publication number: 20250173420
    Abstract: A method of authentication of a first device to a second device uses a signature of an analog signal of the first device. The signature corresponds to a time variation of at least one physical quantity associated with the analog signal during the implementation of at least one specific operation. The at least one specific operation may be an implementation of an electronic function or a program.
    Type: Application
    Filed: November 20, 2024
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Michael PEETERS, Francois DE ROCHEBOUET, Jean-Louis MODAVE
  • Publication number: 20250176235
    Abstract: A method for manufacturing a SiC-based electronic device, comprising the steps of: implanting, on a front side of a solid body made of SiC having a conductivity of an N type, dopant species of a P type thus forming an implanted region, which extends in the solid body starting from the front side and has a top surface coplanar with the front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region to temperatures comprised between 1500° C. and 2600° C. so as to form a carbon-rich electrical-contact region at the implanted region. The carbon-rich electrical-contact region forms an ohmic contact.
    Type: Application
    Filed: January 30, 2025
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Simone RASCUNÁ, Mario Giuseppe SAGGIO, Giovanni FRANCO
  • Publication number: 20250174616
    Abstract: The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.
    Type: Application
    Filed: January 28, 2025
    Publication date: May 29, 2025
    Applicant: STMicroelectronics Pte Ltd
    Inventor: Jing-En LUAN
  • Publication number: 20250174489
    Abstract: The disclosure concerns a method including the steps of: a) providing a structure comprising a semiconductor substrate and, on the side of a first surface of the substrate, at least one first trench filled with an insulating material, vertically extending in the substrate; b) forming, by anisotropic etching from a second surface of the semiconductor substrate opposite to the first surface, at least one second trench vertically extending in the substrate and emerging onto the at least one first trench; and c) widening the at least one second trench by isotropic etching.
    Type: Application
    Filed: March 28, 2023
    Publication date: May 29, 2025
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Thierry BERGER, Jerome DUBOIS, Yann ESCARABAJAL, Patrick GROS D'AILLON
  • Publication number: 20250174269
    Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.
    Type: Application
    Filed: January 23, 2025
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Kedar Janardan DHORI, Harsh RAWAT, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
  • Publication number: 20250176238
    Abstract: A deep trench isolation structure is formed in a semiconductor material body by opening first and second trenches. The sidewalls and bottoms of the first and second trenches are then lined with an insulating material. A halogen-based polymer material is then deposited to cover at least an upper portion of the insulation material in the first trench without covering a portion insulation material at the bottom of the first trench and further cover the insulation material at the sidewalls and bottom of the second trench. An etch process is then used to remove the portion of the insulation material at the bottom of the first trench and the polymer material is removed from both the first trench and second trench. The trenches are then filled with polysilicon to form a substrate plug in the first trench and a field plate electrode in the second trench.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Salvatore Paolo CALABRO', Pietro PETRUZZA, Marta RAIMONDO
  • Publication number: 20250174588
    Abstract: Process for manufacturing electronic components with wettable flanks from a substrate covered by connection terminals and in which chips are formed, the process comprising the following steps: a) solder connection pads to the connection terminals, b) coat the connection pads with a layer of insulating resin, c) thin the insulating resin layer until it reaches the core of the connection pads, d) form cavities by removing part of the connection pads and part of the insulating resin layer, so as to make part of the flanks of the components accessible, e) deposit a layer of conductive material on the flanks of the components and on the connection pads, f) separate the chips.
    Type: Application
    Filed: November 18, 2024
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Ludovic FALLOURD
  • Publication number: 20250176113
    Abstract: A power module including a rigid-flexible PCB that exits from a resin molding case, and includes a first PCB region having a stacked structure of piled up layers; a second PCB region having said stacked structure, further locally delimited at a first side by a top stiffening element and at a second opposite side by a bottom stiffening element; and a third PCB region having said stacked structure without the top and bottom stiffening elements. The top and bottom stiffening elements extend at a lateral surface of the molding case, where the PCB exits from the molding case, and are configured to locally increase the rigidity of the PCB with respect to regions of the PCB 20 where said top and bottom stiffening elements are absent. A power module and method of manufacturing the power module is also provided.
    Type: Application
    Filed: November 15, 2024
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Luciano ZIZZA, Francesco SALAMONE
  • Publication number: 20250175098
    Abstract: The present disclosure is directed to a MEMS device having a first and a second actuator element, of piezoelectric type and a first and a second arm. The first and a second actuator element are configured to generate respective alternate, approximately linear, movements of an own end portion along a first and, respectively, a second direction, the second direction transverse to the first direction. The first arm has a first end rigid with the end portion of the first actuator element. The second arm extends transversally to the first arm and has a first end coupled rigid with the end portion of the second actuator element and a second end coupled rigid with the first arm. The first and the second actuator elements are configured to be driven in an offset manner, so that the second end of the first arm performs a movement along a closed line.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Domenico GIUSTI, Marco FERRERA, Lorenzo TENTORI
  • Publication number: 20250174981
    Abstract: Disclosed is an apparatus including a plurality of channels that drive one or more electrical loads and a control module that generates control signals to operate at least one channel in the plurality of channels, an electronic fuse that monitors one or more operating parameter in a respective channel and detects anomalous conditions in that channel based on the parameter(s) monitored, and a parallel-mode block that defines one or more sets of channels including two or more channels configured to drive a same load. The control module receives from the parallel-mode block parallel-mode management control signals and operates the channels in the set of channels based on parallel-mode management control signals received by the parallel-mode block. The electronic fuse makes the channels in the set of channels non-conductive in response to an anomalous condition detected even in just one channel in the set.
    Type: Application
    Filed: November 18, 2024
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Enrico CASTRO, Calogero Andrea TRECARICHI, Julia CASTELLAN, Philippe BIENVENU
  • Patent number: 12313408
    Abstract: At start-up of a microelectromechanical system (MEMS) gyroscope, the drive signal is inhibited, and the phase, frequency and amplitude of any residual mechanical oscillation is sensed and processed to determine a process path for start-up. In the event that the sensed frequency of the residual mechanical oscillation is a spurious mode frequency and a quality factor of the residual mechanical oscillation is sufficient, an anti-phase signal is applied as the MEMS gyroscope drive signal in order to implement an active dampening of the residual mechanical oscillation. A kicking phase can then be performed to initiate oscillation. Also, in the event that the sensed frequency of the residual mechanical oscillation is a resonant mode frequency with sufficient drive energy, a quadrature phase signal with phase lock loop frequency control and amplitude controlled by the drive energy is applied as the MEMS gyroscope drive signal in order to induce controlled oscillation.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: May 27, 2025
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.r.l.
    Inventors: Yamu Hu, Naren K Sahoo, Pavan Nallamothu, Deyou Fang, David McClure, Marco Garbarino
  • Patent number: 12316731
    Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 27, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Namerita Khanna, Rajnish Garg, Rohit Kumar Gupta
  • Patent number: 12316207
    Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a first path coupled between the input node and a first output node at which a first output voltage is generated, and a second path coupled between the input node and a second output node at which a second output voltage is generated. The DC-DC boost converter operates in a first operating phase where the first path boosts the first output voltage and where the second path is kept from boosting the second output voltage by the second path being coupled to the first path, and operates in a second operating phase where the second path boosts the second output voltage and where the first path is kept from boosting the first output voltage by the second path not being coupled to the first path.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 27, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Aldo Vidoni, Andrea Barbieri, Franco Consiglieri
  • Patent number: 12316325
    Abstract: A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: May 27, 2025
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Giulio Zoppi, Vincent Pascal Onde, Giuseppe Romano
  • Publication number: 20250165163
    Abstract: The present description concerns an operating method of a non-volatile memory, comprising the validation of a transaction, requesting a modification of a value of configuration of a sector of the memory, after comparison of the attributes of the transaction with access attributes of said sector of said memory.
    Type: Application
    Filed: November 6, 2024
    Publication date: May 22, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Jawad BENHAMMADI
  • Publication number: 20250164680
    Abstract: The disclosure relates to an optoelectronic device comprising in a stack: one reflection polarizing filter, one phase-shifting element configured to add a ?/4 phase shift in polarization, one active region, one reflector, so that the light radiation rays reflected by the reflector and passing through the phase-shifting element exhibit a new polarization phase-shifted by ?/2 with respect to their initial polarization, the rays then being reflected anew by the polarizing filter in the direction of the active region.
    Type: Application
    Filed: November 8, 2024
    Publication date: May 22, 2025
    Applicants: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES, STMICROELECTRONICS (GRENOBLE 2) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Raphael MULIN, Olivier JEANNIN, Francois DENEUVILLE
  • Publication number: 20250169153
    Abstract: An electronic component includes a gate structure over a semiconductor layer. The gate structure is insulated from the semiconductor layer and includes a layer made of a magnetic material. The electronic component may form a FET transistor, a MOSFET transistor, a SET transistor, a gated diode, a gated MOS structure, or a gated quantum dot.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 22, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Philippe GALY, Franck SABATIER, Michel PIORO-LADRIERE