Abstract: A circuit detects zero crosses in an input-signal and includes a low-pass-filter (LPF) receiving the input-signal and introducing a phase-shift dependent on the frequency thereof. Filter circuitry receives the output of the LPF, applies a fixed phase-shift thereto, and adjusts phase and DC-offset thereof based on control signals to produce a filtered output-signal. Control circuitry has a zero-crossing detector receiving the input-signal and the filtered output-signal, detecting zero-crossings of the input-signal and the filtered output-signal, asserting a digital zero cross signal at each zero crossing, and determining a phase-shift and DC-offset between the input-signal and filtered output-signal.

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

Abstract: An optical package includes a substrate made of a first material having an upper surface and a lower surface. The substrate further includes at least one cavity opening onto an upper surface of the substrate. Electrical connection vias extend through the substrate. An electronic integrated circuit chip is mounted on the upper surface of the substrate in a position so as to cover the at least one cavity. The electronic integrated circuit chip includes an integrated optical sensor. Each cavity is filled with a second material having a thermal conductivity greater than the thermal conductivity of the first material. The electrical connection vias are arranged on either side of each cavity and between two cavities.

Abstract: An optoelectronic device with a semiconductor body that includes: a bottom cathode structure, formed by a bottom semiconductor material, and having a first type of conductivity; and a buffer region, arranged on the bottom cathode structure and formed by a buffer semiconductor material different from the bottom semiconductor material. The optoelectronic device further includes: a receiver comprising a receiver anode region, which is formed by the bottom semiconductor material, has a second type of conductivity, and extends in the bottom cathode structure; and an emitter, which is arranged on the buffer region and includes a semiconductor junction formed at least in part by a top semiconductor material, different from the bottom semiconductor material.

Abstract: The integrated circuit includes a power amplifier, an antenna, and a matching and filtering network including a direct current power supply stage on an output node of the power amplifier, a first section, and a second section. The direct current power supply stage and the two sections include inductor-capacitor “LC” arrangements configured to have an impedance that is matched to the output of the power amplifier in the fundamental frequency band. The LC arrangements of the direct current power supply stage and of the first section are furthermore configured to have resonant frequencies that are respectively adapted to attenuate harmonic frequency bands of the fundamental frequency band.

Abstract: A microelectromechanical mirror device includes a supporting frame of semiconductor material and a plate of semiconductor material. The plate is connected to the supporting frame so as to be orientable around at least one rotation axis. A reflective layer is arranged on a first region of the plate. A piezoelectric actuation structure extends on a second region of the plate adjacent to the reflective layer. The piezoelectric actuation structure is configured to apply forces such as to modify a curvature of the plate.

Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

Abstract: In an embodiment a method for managing a low-power mode of an electronic device includes at a first request for transitioning an electronic device to a low-power mode, storing values of a first counter and a second counter of the electronic device on a first edge of a first clock and at a second request for transitioning the electronic device out of the low-power mode calculating a number of periods of a second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge and updating the value of the second counter with a calculated value, wherein the first clock drives the first counter and the second clock drives the second counter, the second clock being faster than the first clock.

Abstract: A system-on-a-chip includes a first digital domain and a second digital domain. An interface circuit includes a level-shifting circuit for converting a signal between the first digital domain and the second digital domain. The first digital domain includes a control circuit configured to generate a control signal for transmission to the second digital domain. The control signal includes a pulse having a nominal duration adapted to the level-shifting circuit. At the input of the level-shifting circuit, the interface circuit includes, in the first domain, a conditional pulse-stretching circuit that lengthens a duration of the pulse of the control signal to at least the nominal duration when a duration of the pulse of the control signal is shorter than the nominal duration and non-zero.

Abstract: An electronic vehicle includes A DC link capacitor and a traction inverter coupled to the DC link capacitor. The traction inverter includes a first half bridge circuit, a second half bridge circuit, and a third half bridge circuit each coupled between terminals of the DC link capacitor. The traction inverter includes a driver circuit coupled to the traction inverter configured to drive the first, second, and third half bridge circuits to generate an AC voltage in a standard operating mode. The driver circuit is configured to discharge the DC link capacitor responsive to a discharge command by toggling the first half bridge between an open condition and a closed condition while holding the second half bridge circuit and the third half bridge circuit in the open condition.

Abstract: An electronic digital system includes a digital core and a Serializer Deserializer module. A FIFO device of the core reads and writes on a set of buses coupled to said Serializer Deserializer module. The Serializer Deserializer module transmits data read from the FIFO architecture device on a set of buses as a corresponding serial signals transmitted by transmitters. The serial signals and corresponding transmitters are logically grouped. The transmitters include PLL circuits generating PLL clocks, using as reference a cluster transmitter reference clock common, to a respective cluster of transmitters controlling a frequency of serialization operation and low frequency clocks obtained by the PLL clocks according to one or more groups corresponding to group of buses.

Abstract: A MOSFET transistor with a semiconductor body including a drain region of a first conductivity type, delimited by a front surface, and at least one cell including: a pair of gate structures laterally offset parallel to a first axis and each including a respective gate dielectric region, arranged on the front surface, and a respective gate conductive region, arranged on the corresponding gate dielectric region; a body structure of a second conductivity type, which includes a body region, which extends inside the drain region starting from the front surface and contacts portions of the gate dielectric regions, and a strengthening region, which extends below the body region; and a pair of source regions of the first conductivity type, which extend inside the body region starting from the front surface.

Abstract: A process for forming a high electron mobility transistor (HEMT) includes forming a semiconductor heterostructure including a channel layer of the HEMT, forming a gate layer of GaN on the channel layer, and patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. The process includes forming an isolation mask covering an active region of the semiconductor heterostructure and the gate arc and performing an ion bombardment process on an inactive region of the semiconductor heterostructure exposed by the isolation mask.

Abstract: A method, comprising: coupling a set of sensing circuits to a set of electronic devices; sensing, via the sensing circuits, a set of sensing signals indicative of an operating state of the set of electronic devices; applying logic signal processing to the set of sensing signals via coupling a set of signal processing channels to the set of sensing circuits and providing a set of logically combined sensing signals as a result, wherein the logically combined sensing signals are indicative of whether the operating state of the electronic devices in the set of electronic devices is an expected operating state or an unexpected operating state; coupling the set of logically combined sensing signals to a set of input channels of a fault collection and control unit, FCCU; storing at least one data structure comprising data related to the way in which the set of input channels of the FCCU are coupled to the set of sensing circuits via the set of signal processing channels.

Abstract: The present disclosure is directed to cough detection for electronic devices, such as wireless headphones. The cough detection utilizes inertial sensors to perform both head movement detection and vocal activity detection. The dual identification of head movement and vocal activity allows improved detection accuracy, and minimal false detections caused by environmental noise.

Abstract: The present description relates to a method of manufacturing an electronic device comprising a phase-change memory cell, the method comprising: the forming of a first layer made of a resistive material; the forming of a stack of layers on the first layer, the stack comprising at least one second layer made of a phase-change material; the etching of the stack, said etching stopping when the first layer is reached around the location of the memory cell; the forming of a spacer on the side walls of the stack; then an etching of the first layer, so that the stack rests on a central portion of the first layer and that the spacer rests on a peripheral portion of the first layer.

Abstract: A band-gap circuit for generating a bandgap reference signal includes a first bipolar transistor and a second bipolar transistor of a same type among PNP and NPN types. The first and second bipolar transistors are configured to generate a current varying proportionally with the temperature. A capacitor is connected between a base and an emitter of one or both of the first and second bipolar transistors.

Abstract: A system to sanitize a surface includes an emitter. The emitter of the system to sanitize the surface includes: a light source configured to generate light at a sanitizing wavelength; a receiver configured to receive a wireless signal; and a processing circuit for the emitter configured to turn the light source on, turn the light source off, and adjust an intensity of light generated by the light source depending on the wireless signal. The system to sanitize the surface further includes a sensor. The sensor of the system to sanitize the surface includes: a photoelectric transducer configured to convert light at the sanitizing wavelength to a current; and a processing circuit for the sensor powered by the current and in communication with a transmitter to transmit the wireless signal, the processing circuit for the sensor being configured to control emission of the wireless signal depending on a power level supplied by the current.

Abstract: An electronic device includes a carrier substrate having a front face and an electronic chip mounted on the front face. An encapsulation cover is mounted above the front face and bounds a chamber in which the chip is situated. A front opening is provided in front of an optical component of the chip. An optical element, designed to allow light to pass, is mounted on the cover in a position which covers the front opening of the cover. The optical element includes a central region designed to deviate light and a positioning pattern that is visible through the front opening. An additional mask is mounted on the encapsulation cover in a position which extends in front of the optical element. A local opening of the additional mask is situated in front of the optical component.

Abstract: A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.