Abstract: A process for a slave device on a serial data bus to make an in-band interrupt request to a master device includes checking whether a backoff time stored by a backoff timer has expired. When the backoff time has not expired, the slave device refrains from initiating the in-band interrupt request to the master device in response to a start condition on the serial bus. However, when the backoff time has expired, the slave device is permitted to initiate the in-band interrupt request to the master device in response to the start condition on the serial bus.

Abstract: A device includes a leadframe with a semiconductor die having a first side facing and electrically coupled to the leadframe and a second side facing away from the leadframe. An encapsulation body containing laser direct structuring (LDS) material covers the semiconductor die and has an outer surface opposite the leadframe. Metal vias are formed through the LDS material between the outer surface and the second side of the semiconductor die, and a metal pad is formed at the outer surface. The metal vias and pad create a thermal dissipation path. The semiconductor die may be mounted in a flip-chip configuration and connected to the leadframe through metal pillars. The metal vias and pad may be formed by laser-activating the LDS material followed by copper plating. The device can be configured as a Quad Flat No-leads (QFN) package, and a heat sink may be mounted on the metal pad.

Abstract: A half bridge circuit includes two GaN high electron mobility transistors (HEMT). A driver circuit generates a high side and low side driver signals corresponding to square wave. A driver deadtime is the period between during which both driver signals are low. A half bridge adjustment circuit is coupled between the driver and the half bridge circuit and generates a modified high side driver signal and a modified low side driver signal, each including a transition from a low voltage to an intermediate voltage during the corresponding deadtime and a transition from the intermediate voltage to a high voltage at an end of the corresponding deadtime. The half bridge adjustment circuit drives the gate terminals of the high side and low side transistors with the modified high side and low side driver signals.

Abstract: A substrate includes a center portion and a peripheral portion connected to the center portion by a flexible coupling region. A first die is mounted to an upper surface of the substrate at the center portion and a second die is mounted to the upper surface of the substrate at the peripheral portion. A heatsink includes a base plate, fins extending from an upper surface of the base plate and tabs extending from a lower surface of the base plate. The tabs of the heatsink are mounted to the upper surface of the substrate at the center portion, and the lower surface of the base plate is thermally coupled to a back of the first die. The peripheral portion is folded relative to the center portion at the flexible coupling region. An outer surface of the fin of the heatsink is thermally coupled to a back of the second device.

Abstract: The present description concerns a method of manufacturing an electronic circuit comprising, in the order, the forming on a semiconductor substrate comprising a surface of at least one conductive pad extending over the surface and having sides inclined with respect to the surface, the forming of a first insulating layer on the pad, the deposition of a resin layer and the forming of an opening in the resin layer exposing the entire pad, the plasma etching of the first insulating layer in the opening, which results in the forming of first compounds on the etched edges of the first insulating layer and of second compounds on the pad, the removal of the resin layer, the removal of the first compounds, the removal of the second compounds, and the forming of a second insulating layer on the pad.

Abstract: A process that helps ensure uniform height of conductive structures formed among intermetal dielectric layers of a wafer. When a metal layer is deposited on a first intermetal dielectric layer, a sealing layer is formed on the metal layer either before or after the metal layer is patterned to form metal interconnect structures. A first interlevel dielectric sub-layer is then formed on the sealing layer. A chemical mechanical planarization (CMP) process is then performed on the first interlevel dielectric sub-layer using the sealing layer as an etch stop. A second interlevel dielectric sub-layer is then formed on the first interlevel dielectric sub-layer.

Abstract: Packaged electronic device, having a C-shaped leadframe including a base section and a pair of transverse sections extending transversely to the base section. A first die and a second die have a first contact region at a first main surface and a second contact region at the second main surface; the first main surfaces of the first and the second dice are attached to a first face of the base section of the leadframe. A first lead is coupled to the second contact region of the first die and has a first external contact portion. A second lead is coupled to the second contact region of the second die and has a second external contact portion. A packaging mass surrounds the leadframe, the first lead and the second lead, embeds the first and the second dice and extends level with the base section and with the transverse sections of the leadframe as well as with the external contact portions of the leads.

Abstract: The present description concerns a method of configuration of a phase-change non-volatile memory, comprising the partitioning of said memory into a first set of one or a plurality of regions having a first maximum number of write cycles and a second set of one or a plurality of other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, the first and second maximum number of write cycles being linked to different physical write parameters.

Abstract: A DC-DC switching converter includes an electrical network with an inductor, switches and first and second capacitors subject to first and second voltages. A control module generates first and second control signals to control the switches with a sequence of switching periods implementing, for each switching period, a phase succession including: an inductor charge phase having a first duration as a function of the first control signal; a first inductor discharge phase towards the first capacitor having a second duration as a function of the second control signal; and a second inductor discharge phase towards the second capacitor. The control module couples to the electrical network to form a signal vector including signals indicative of the first and second voltages and the current. A gain stage generates the first and second control signals by multiplying the signal vector by a gain matrix for the control module forming a linear-quadratic regulator.

Abstract: First digital-components are clocked by a system-clock, and second digital-components are clocked by a gated system-clock. A detection-module identifies detection-events and generates an event-flag in response. A digital-comparator generates a comparator-output based upon comparison of a count-value with a threshold, the comparator-output asserted when the count-value is less than the threshold and is deasserted when the count-value is equal-to or greater-than the threshold. A counter sets the count-value to a predetermined-value upon receipt of the event-flag, and, in response to assertion of the comparator-output, increments the count-value upon each successive rising-edge of the system-clock, but ceases when the comparator-output is deasserted.

Abstract: A thermoelectric unit includes a thermoelectric membrane having a first surface at a cavity in a layer of first thermally conductive material. The thermoelectric membrane has a second surface opposite to the first surface with second thermally conductive material arranged in contact with the second surface of the thermoelectric membrane. The thermoelectric membrane includes thermally sensitive material configured to generate via the Seebeck effect a thermoelectric signal indicative of the temperature difference between the second thermally conductive material and the first thermally conductive material. An insulating molding compound is molded onto the second thermally conductive material arranged in contact with the second surface of the thermoelectric membrane wherein mechanical stress develops in the thermoelectric membrane in response to molding. An encapsulation is provided at the second surface of the thermoelectric membrane.

Abstract: An integrated circuit chip includes a first pad coupled to an external power supply voltage by a conductive wire; a PMOS transistor coupling the first pad to an internal node; a second pad coupled to an external reference voltage by another conductive wire; and a capacitor coupling said first and second pads. A sensing circuit detects an increase in a drain-source resistance of the transistor. A control circuit supplies, during each switching of the transistor to the off state, a first current to the gate of the transistor until the sensing circuit detects the increase in the drain-source resistance, then supplies a second current lower than the first current.

Abstract: Wafer level testing is performed on a wafer including integrated circuit dies, each integrated circuit die including a die pads, with each die pad covered by a protection layer. The wafer level testing includes, at a given die pad: puncturing through the protection layer with a distal end of a probe to make physical and electrical contact with the given die pad at a first location at the given die pad; performing a first electrical test of the integrated circuit die through the probe; horizontally translating after completion of the first electrical test; puncturing through the protection layer with the distal end of the probe to make physical and electrical contact with the given die pad at a second location, different from the first location, at the given die pad; and performing a second first electrical test of the integrated circuit die through the probe.

Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.

Abstract: A leadframe includes first leads and second leads, wherein each lead of the first and second leads has an upper surface. First and second silver spots are provided on the upper surface of each lead of the first and second leads. An integrated circuit die has a front surface including first and second interconnection pads. A first pillar is mounted to each first interconnection pad, and second pillar is mounted to each second interconnection pad. The integrated circuit die is mounted in flip chip orientation to the leadframe with the first pillars soldered to the first silver spots and the second pillars soldered to the second silver spots. A resin body encapsulates the integrated circuit die mounted to the leadframe.

Abstract: A clock signal detection circuit includes a first input that receives an always-on clock signal, and a second input that receives an activatable clock signal. A detection flip-flop circuit has a data input terminal that receives an always-high logic signal, a clock terminal that receives the always-on clock signal, a reset terminal that receives a reset signal, and a data output terminal that produces an asynchronous clock detection signal. The reset signal is asserted to reset the detection flip-flop circuit in response to the activatable clock signal being asserted, and the reset signal is de-asserted to prevent reset of the detection flip-flop circuit in response to the activatable clock signal being de-asserted. The asynchronous clock detection signal is passed to an output to provide a clock detection signal that is asserted to indicate that the activatable clock signal is absent.

Abstract: A system includes a memory and a processor coupled to the memory. The processor executes an instruction set having a word size. The processor includes arithmetic processing circuitry, which, in operation, executes arithmetic operations on operands having the word size. The arithmetic processing circuitry includes an arithmetic logic circuit (ALU) having an operand size smaller than the word size of the instruction set. The ALU, in operation, generates partial results of the arithmetic operations. A multiplexing network coupled to inputs of the ALU provides portions of the operands to the ALU. A shift register having the word size of the instruction set accumulates partial results generated by the ALU over a plurality of clock cycles and outputs results of the arithmetic operations based on the accumulated partial results.

Abstract: The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

Abstract: A method for estimating a flicker frequency of a light source includes: obtaining, with a time-of-flight sensor, a profile of a light signal emitted by a light source; performing spectral analysis on the profile of the light signal emitted by the light source; and estimating a flicker frequency of the light source based on the spectral analysis of the profile of the light signal emitted by the light source.

Abstract: In an embodiment, a circuit includes cascaded delay units arranged in a chain, each delay unit having an input-to-output delay time, wherein a first delay unit in the chain is configured to receive an input signal for propagating along the delay units in the chain, logic circuitry coupled to delay units in the chain, the logic circuitry configured to generate a clock signal as a logic combination of signals input to and output from the delay units in the chain and feedback circuitry configured to supply to the first delay unit in the chain a feedback signal, the feedback circuitry including a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit arranged between the first delay unit in the chain and the last delay unit in the chain.