Abstract: A first element and a second element of a same device communicate with each other. The first element sends the second element a first piece of information representative of energy supplied by an electromagnetic field supplying power the device. The second element adapts its operating frequency as a function of the first piece of information.

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: An electronic device is couplable to a plurality of laser diodes and includes a control switch having a drain coupled to a drain metallization and having a source coupled to a first source metallization that is electrically couplable to cathodes of the laser diodes. Each of a plurality of first switches has a drain coupled to the drain metallization and a source coupled to a respective second source metallization that is couplable to an anode of the laser diodes. The second source metallizations are aligned with one another in a direction of alignment, overlie, in a direction orthogonal to the direction of alignment, the respective sources of the first switches, and can be aligned, in a direction orthogonal to the direction of alignment, to the respective laser diodes. At least one of the sources of the first switches can be aligned, in a direction orthogonal to the direction of alignment, to the respective laser diode.

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm. For each substitution operation of the cryptographic algorithm, a series of substitution operations are performed by the cryptographic circuit. One of the substitution operations of the series is a real substitution operation corresponding to the substitution operation of the cryptographic algorithm. One or more other substitution operations of the series are dummy substitution operations. A position of the real substitution operation in said series is selected randomly.

Abstract: A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.

Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.

Abstract: A closed container includes a detection device for detecting opening of or an attempt to open the container. The detection device includes a contactless passive transponder that is configured to communicate with a reader via an antenna using a carrier signal. An integrated circuit of the transponder includes two input terminals connected to the antenna and two output terminals linked by a first electrically conductive wire having a severable part which is severed in the event of an opening of or an attempted opening of the container. A shorting circuit is configured to short-circuit a first output terminal with a first input terminal in the event of a conductive repair of the severed part which forms an electrical connection between the two output terminals.

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Abstract: A microcontroller is capable of executing a process that is parameterizable by at least one parameter. The microcontroller includes a processor and a hardware module coupled to the processor. The hardware module is configured to hardware execute the process and the processor is configured to deliver the at least one parameter to the hardware module.

Abstract: A method can be used monitoring a task for an electronic module. The method includes waiting for performance of the task, timing the wait, the timing being regulated by a clock signal and generating an alert signal when the timing of the wait has exceeded a reference value. The device can be part of a multimedia interface (e.g., a display) electronic module and the task a graphical task (e.g., an image refresh).

Abstract: A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.

Abstract: A cryptographic device includes hardware data processing circuitry and software data processing circuitry coupled to the hardware data processing circuitry. The device, in operation, executes a plurality of rounds of a symmetrical data cipher algorithm and protects the execution of the plurality of rounds of the symmetrical data cipher algorithm. The protecting includes executing data masking and unmasking operations using the hardware data processing circuitry, executing linear operations applied to data using the software data processing circuitry, executing linear operations applied to masks using the hardware data processing circuitry, and executing non-linear operations applied to data using one of the hardware data processing circuitry or the software data processing circuitry.

Abstract: A method of detecting a cold-boot attack on an integrated circuit, including the steps of: periodically sampling a signal delivered by at least one ring oscillator; and verifying that the proportion of states “1” and of states “0” of the result of the sampling is within a range of values.

Abstract: A device includes image generation circuitry and convolutional-neural-network circuitry. The image generation circuitry, in operation, generates a digital image representation of a wafer defect map (WDM). The convolutional-neural-network circuitry, in operation, generates a defect classification associated with the WDM based on: the digital image representation of the WDM and a data-driven model associating WDM images with classes of a defined set of classes of wafer defects and generated using a training data set augmented based on defect pattern orientation types associated with training images.

Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.

Abstract: An integrated physical unclonable function device includes at least one reference capacitor and a number of comparison capacitors. A capacitance determination circuit operates to determine a capacitance of the at least one reference capacitor and a capacitance of each comparison capacitor. The determined capacitances of the comparison capacitors are then compared to the determined capacitance of the reference capacitor by a comparison circuit. A digital word is then generated with bit values indicative of a result of the comparisons made by the comparison circuit.

Abstract: A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.

Abstract: The disclosure concerns an electronic chip including a resistive region and a first switch of selection of a first area in contact with the resistive region.