Patents Assigned to STMicroelectronics (Rousset) SAS
  • Method for writing in EEPROM memory and corresponding integrated circuit
    Patent number: 11120878
    Abstract: A method for programming a non-volatile memory (NVM) and an integrated circuit is disclosed. In an embodiment an integrated circuit includes a memory plane organized into rows and columns of memory words, each memory word comprising memory cells and each memory cell including a state transistor having a control gate and a floating gate and write circuitry configured to program a selected memory word during a programming phase by applying a first nonzero positive voltage to control gates of the state transistors of the memory cells that do not belong to the selected memory word.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 14, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Method for writing in a volatile memory and corresponding integrated circuit
    Patent number: 11120887
    Abstract: An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: September 14, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christophe Eva, Jean-Michel Gril-Maffre
  • PHASE-CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE
    Publication number: 20210280779
    Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe BOIVIN, Simon JEANNOT
  • METHOD FOR WRITING DATA IN A MEMORY OF A CONTACTLESS TRANSPONDER, AND CORRESPONDING CONTACTLESS TRANSPONDER DEVICE
    Publication number: 20210280228
    Abstract: A contactless transponder includes a non-volatile static random access memory including memory points. Each memory point is formed by a volatile memory cell and a non-volatile memory cell. A protocol processing circuit receives data and stores the received data in the volatile memory cells of the memory. A write processing circuit is configured, at the end of the reception and storage of the data, to record, in a single write cycle, the data from the volatile memory cells to the non-volatile memory cells of the respective memory points.
    Type: Application
    Filed: March 1, 2021
    Publication date: September 9, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Francois TAILLIET, Beatrice BROCHIER, Sylvain FIDELIS
  • Method for managing the startup of a phase-locked loop and corresponding integrated circuit
    Patent number: 11115038
    Abstract: The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 7, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Laurent Truphemus, Christophe Eva
  • Resistive memory cell having an ovonic threshold switch
    Patent number: 11114502
    Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 7, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Philippe Boivin
  • Stack overflow protection by monitoring addresses of a stack of multi-bit protection codes
    Patent number: 11113384
    Abstract: A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in an internal memory coupled to the processing unit. Comparators in the hardware monitor circuit are arranged to accept values from the internal memory and gating logic coupled to the comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 7, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pierre Guillemin, William Orlando
  • Error detection
    Patent number: 11115061
    Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 7, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Fabrice Romain, Mathieu Lisart, Patrick Arnould
  • Process for fabricating resistive memory cells
    Patent number: 11114614
    Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 7, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Boivin
  • Method for compensating for a phase shift between the signal emitted by an object and that received from a reader equipped with an envelope detector and corresponding object
    Patent number: 11100299
    Abstract: An operation of calibrating the object using a reference reader is performed, the calibration operation including an operation of placing the reference reader at various distances away from the object that correspond to various values of a parameter within the object that is representative of the intensity of the signal received by the object, and, for each distance, an operation of determining an internal phase-shift compensation in the object with respect to a nominal internal phase shift, making it possible to obtain a load modulation amplitude that is higher, in terms of absolute value, than a threshold, and an operation of storing a lookup table of the various values of the parameter and the corresponding internal phase-shift compensations.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 24, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Nicolas Cordier, Anthony Tornambe
  • SERIAL DATA INTERFACE WITH REDUCED LOOP DELAY
    Publication number: 20210248104
    Abstract: A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.
    Type: Application
    Filed: January 7, 2021
    Publication date: August 12, 2021
    Applicants: STMicroelectronics International N.V., STMicroelectronics (Rousset) SAS
    Inventors: Manoj KUMAR, Kailash KUMAR, Nicolas DEMANGE
  • Pin diode including a conductive layer, and fabrication process
    Patent number: 11088241
    Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 10, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Method for managing an update of a microcode within a processing unit
    Patent number: 11086622
    Abstract: Microcode is stored in a program memory and intended to be executed by a central processing unit of a processing unit. The processing unit may include a memory controller associated with each program memory and a hardware peripheral. The method includes, in response to a request to update the microcode, a transmission, to each hardware peripheral, of a global authorization request signal obtained from an elementary authorization request signal generated by each corresponding memory controller, a transmission of a global authorization signal obtained from an elementary authorization signal generated by each hardware peripheral in response to the global authorization request signal and after satisfying a predetermined elementary condition, and an updating of each microcode by the corresponding memory controller only after the global authorization signal is received.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: August 10, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Vincent Onde
  • Device and method for NFC device charging
    Patent number: 11088726
    Abstract: The present disclosure relates to a detection method or device, by a first NFC device generating an electromagnetic field for recharging a battery of a second NFC device, of a disruptive condition, in which thresholds (MHTH, MLTH, PHTH, PLTH) for detection of a variation of the field are adjusted in real time during the recharging.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: August 10, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • Circuit and method for protecting a voltage regulating circuit against electrostatic discharges
    Patent number: 11088536
    Abstract: An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 10, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Nicolas Demange
  • MICROCONTROLLER COMPRISING OSCILLATORS THAT ARE CONFIGURED TO RECEIVE EXTERNAL RESONATOR SIGNALS
    Publication number: 20210242834
    Abstract: A shared pair of input/output cells configured to be able to be connected to a first external resonator or a second external resonator. A first oscillator and a second oscillator are coupled to the shared pair input/output cells by a switching circuit. The switching circuit is configured to be able to connect either the first oscillator or the second oscillator to the pair of input/output cells.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 5, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Arnaud GAMET, Philippe LE FEVRE
  • OVERVOLTAGE PROTECTION
    Publication number: 20210242679
    Abstract: The present disclosure relates to a device including a rectifying bridge including: a branch connected between first and second nodes; another branch including first and second MOS transistors series-connected between the first and second nodes and having their sources coupled together; a resistor connecting the gate of the first transistor to the second node; another resistor connecting the gate of the second transistor and the first node; and for each transistor, a circuit including first and second terminals respectively connected to the drain and to the gate of the transistor, and being configured to electrically couple its first and second terminals when a voltage between the first terminal of the circuit and the first terminal of the other circuit is greater than a threshold of the circuit.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Integrated circuit with vertically structured capacitive element, and its fabricating process
    Patent number: 11081488
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 3, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel, Quentin Hubert, Thomas Cabout
  • Memory architecture of a near-field communication device
    Patent number: 11082092
    Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 3, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Sylvie Wuidart, Sophie Maurice
  • Device for determining the movement of a rotary element, particularly for readings of water and/or gas meters
    Patent number: 11079256
    Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: August 3, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Vincent Onde