Patents Assigned to STMicroelectronics (Rousset) SAS
  • ERROR DETECTION
    Publication number: 20210367619
    Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Fabrice ROMAIN, Mathieu LISART, Patrick ARNOULD
  • Process for fabricating medium-voltage transistors and corresponding integrated circuit
    Patent number: 11183505
    Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: November 23, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Franck Julien, Abderrezak Marzaki
  • Power-on-reset circuit and corresponding electronic device
    Patent number: 11171644
    Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: November 9, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Antonino Conte, Francesco Tomaiuolo, Francesco La Rosa
  • Method for manufacturing a capacitive element having electrical coupling the first electrode to the active region
    Patent number: 11164875
    Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 2, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • PIN DIODE INCLUDING A CONDUCTIVE LAYER, AND FABRICATION PROCESS
    Publication number: 20210335994
    Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 28, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal FORNARA
  • MEMORY ARCHITECTURE OF A NEAR-FIELD COMMUNICATION DEVICE
    Publication number: 20210328627
    Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Sylvie WUIDART, Sophie MAURICE
  • Integrated circuit including bipolar transistors
    Patent number: 11152430
    Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: October 19, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
  • Method for communication between circuits
    Patent number: 11151435
    Abstract: A first element and a second element of a same device communicate with each other. The first element sends the second element a first piece of information representative of energy supplied by an electromagnetic field supplying power the device. The second element adapts its operating frequency as a function of the first piece of information.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Julien Mercier
  • Method for managing a return of a product for analysis and corresponding product
    Patent number: 11143701
    Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 12, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche
  • INTEGRATED CIRCUIT PROVIDED WITH DECOYS AGAINST REVERSE ENGINEERING AND CORRESPONDING FABRICATION PROCESS
    Publication number: 20210313280
    Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 7, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak MARZAKI, Mathieu LISART
  • Integrated circuit with vertically structured capacitive element, and its fabricating process
    Patent number: 11139303
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: October 5, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel, Quentin Hubert, Thomas Cabout
  • Protection of integrated circuits
    Patent number: 11139255
    Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 5, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Denis Farison, Romain Coffy, Jean-Michel Riviere
  • Device comprising a start-up circuit, and method of manufacturing thereof
    Patent number: 11137786
    Abstract: An electronic device includes a starting circuit configured to compare a value representative of the power supply voltage with a threshold, wherein the circuit includes a generator of a current proportional to temperature.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: October 5, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Jimmy Fort, Maud Pierrel, Nicolas Borrel, Thierry Soude
  • Method for precharging an integrated-circuit supply, and corresponding integrated circuit
    Patent number: 11139676
    Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: October 5, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Laurent Truphemus, Sebastien Ortet
  • MICROCIRCUIT CARD
    Publication number: 20210303960
    Abstract: A microcircuit card includes a first (general purpose) microcontroller, a second (secure processing) microcontroller, at least one module of communication with the outside of the card, and a biometric sensor. Any communication with the outside of the card transits through the first microcontroller. Any communication between the sensor and the second microcontroller transits through the first microcontroller. Furthermore, the second microcontroller is not involved in any communication to the outside of the card.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 30, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Olivier ROUY
  • Switchable diode devices having transistors in series
    Patent number: 11133798
    Abstract: A device includes a first connection pin, a second connection pin, a third connection pin, and a fourth connection pin. The second connection pin is configured to be connected to a supply voltage. The fourth connection pin is configured to be coupled to a reference voltage. The device further includes a first transistor including: a first gate and a first source/drain coupled to the first connection pin; a second transistor including a second gate and a second source/drain connected to the first transistor; and a third transistor including a third gate, a third source/drain connected to the second transistor, and a fourth source/drain connected to the fourth connection pin. The third transistor is configured to be controlled by a digital signal using the third connection pin. Both the first gate and the second gate are directly connected to the second connection pin.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 28, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Nicolas Froidevaux, Laurent Lopez
  • Method for adjusting phase in contactless communication
    Patent number: 11126805
    Abstract: An object is capable of contactless communication with a reader by active charge modulation. The object includes an antenna, an impedance matching circuit, a memory, and a controller connected to the antenna through the impedance matching circuit. The antenna, the an impedance matching circuit and the controller together form a resonant circuit having a resonant frequency. The controller is configured to cause the object to transmit, in the absence of a signal received from a reader, a signal at the resonant frequency, to determine a characteristic obtained from the signal uniquely transmitted by the object, and to perform an adjustment of a phase shift within the object based on the characteristic and an indication stored in the memory, the indication linking values of phase shifts with values of the characteristic.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 21, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Anthony Tornambe, Nicolas Cordier
  • Method for addressing a non-volatile memory on IC bus and corresponding memory device
    Patent number: 11127468
    Abstract: Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 21, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • INTEGRATED CAPACITIVE ELEMENT AND CORRESPONDING PRODUCTION METHOD
    Publication number: 20210288189
    Abstract: An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 16, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • Production of semiconductor regions in an electronic chip
    Patent number: 11121042
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: September 14, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Franck Julien, Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret