Abstract: A circuit is provided for supplying a load from an AC voltage supply. The circuit includes a control circuit and a bidirectional switch coupled in series with the load. The bidirectional switch includes two one-way switches connected in antiparallel, and the control circuit controls the bidirectional switch based on a relatively low DC voltage. The bidirectional switch is connected to a first terminal of the AC voltage supply, and the DC voltage is referenced to the first terminal of the AC voltage supply. Additionally, an apparatus connected to an AC voltage supply and a relatively low DC voltage is provided. The apparatus includes a control circuit, a load to be supplied by the AC voltage supply, and a bidirectional switch coupled in series with the load. The bidirectional switch includes two one-way switches connected in antiparallel, and the control circuit controls the bidirectional switch based on the DC voltage.

Abstract: A carrier of semiconductor wafer transportation. The carrier comprising: a base; two or more walls mounted to the base, with a plurality of grooves for receiving wafers by lateral insertion thereinto through a mouth, the mouth defined by an upper wall and a substantially horizontal lower wall, wherein the groove comprises a closed end defined by a back wall joined to the upper wall and the lower wall so that the groove narrows from the mouth towards the closed end, the upper wall being slanted upward towards the mouth and the back wall being slanted towards the mouth in the region close to the horizontal wall.

Abstract: The present invention relates to a phase-locked loop circuit including: a programmable ring oscillator generating drive signals, an assembly of latches receiving an input signal of the circuit, the latches being driven by the drive signals and generating samples by sampling of the input signal, and a logic decoding circuit receiving samples generated by latches and accordingly driving the oscillator.

Abstract: A method of forming an insulated well in an upper portion of a silicon substrate, including the steps of providing a structure of silicon-on-insulator type including a silicon substrate, an insulating layer, and a thin single-crystal silicon layer; removing the insulating layer and the thin silicon layer outside locations where the insulated well is desired to be formed; growing an epitaxial layer; performing a planarization; and making a vertical insulating wall above the periphery of the maintained portion of the thin insulating layer.

Abstract: A one-time programmable cell including an inverter providing a logic state according to the state of the cell; a fuse coupled between a first supply voltage and the inverter input; and a current source coupled between the fuse and a second supply voltage. The inverter is supplied from the second supply voltage through a first diode-connected transistor and the current source is formed of a second transistor controlled by the inverter output, this second transistor having a threshold voltage greater than that of the first transistor.

Abstract: The present invention relates to a method of cleaning of a semiconductor wafer covered with silicon oxide, topped with an aluminum layer in which patterns are formed by plasma etching of the aluminum, this etching causing the formation of a polymer containing, in particular, aluminum and carbon on the substantially vertical walls of the patterns, including rotating the wafer in its plane around its axis, in an enclosure under a controlled atmosphere, at ambient temperature, including the following steps rotating the wafer at a speed between 500 and 2000 rpm in an enclosure filled with nitrogen; sprinkling the wafer with water, substantially at the center of the wafer; introducing hydrofluoric acid during a determined cleaning time, while maintaining the sprinkling; and rinsing the wafer by continuing the sprinkling to remove any trace of hydrofluoric acid from the wafer, at the end of the cleaning time.

Abstract: A device for the generation of a drive signal phase-shifted with respect to an external synchronization signal includes a first digital phase-locked loop to give a reference signal, servo-linked to the external synchronization signal by a current phase among N phases of a high frequency signal. The device includes a second digital phase-locked loop including a measuring circuit to measure the position of an active edge of the drive signal or a derived signal that is delayed with respect to an active edge of the reference signal. The second phase-locked loop also includes a circuit to compute the phase shift to be made and a phase-shift circuit. The measurement circuit includes a circuit for the rough measurement of the position, controlled by a fixed phase of the high frequency signal independent of the present phase of locking in the first loop. The digital computation circuit accounts for this shift between the fixed phase and the present phase.

Abstract: A device is provided for neutralizing an electronic circuit whose rate is set by a clock signal in the event of an anomaly in the clock signal. The device includes an inhibition circuit for selectively inhibiting operation of the electronic circuit, and an anomaly detector for activating the inhibition circuit to inhibit operation of the electronic circuit as soon as an anomaly is detected in the clock signal. In one preferred embodiment, the anomaly detector includes two monostable circuits and a logic circuit. The first monostable circuit receives the clock signal and outputs a first pulse at each trailing edge of the clock signal, and the second monostable circuit receives the clock signal and outputs a second pulse at each leading edge of the clock signal. The logic circuit receives the first and second pulses and outputs an activation signal to the inhibition circuit whenever the clock signal shows an anomaly.

Abstract: A bandpass filter includes a first and a second transconductor. The first transconductor has a first input connected to ground, and a second input connected to a second input of the second transconductor and to the output of the filter. An output of the first transconductor is connected to a first input of the second transconductor, and to an input of a filter through a first capactor. The output of the second transconductor is connected to ground through a second capacitor, and to a monitor amplifier. An output of the monitor amplifier is connected to the output of the filter. The bandpass filter further includes a third capacitor arranged between the second input and the output of the first transconductor, and a splitter bridge connected to the second input of the second transconductor.

Abstract: A method for testing an integrated circuit comprising an input capacitance designed to form, with an antenna coil, a resonant receiver circuit with a predetermined natural frequency. The input capacitance is connected to a test inductance chosen to form, with the input capacitance, a resonant test circuit having a resonant frequency substantially equal to the natural frequency of the resonant receiver circuit. The resonant test circuit is excited by an alternating signal provided through a transformer. The testing of inductive integrated circuits working without contact is implemented in a corresponding test system.

Abstract: To accelerate read operations, or the operations that modify the operating parameters of a microcontroller, an interface is provided with three registers—an address register, an instruction and data register, and an auxiliary register. The instruction and data register supports the auxiliary register by indirect addressing. The address register is furthermore provided with an incrementation circuit mechanism for indirect incrementation. With the indirect addressing and the automatic incrementation, the number of external operations are reduced for continuous read or write operations.

Abstract: Each memory cell of the memory includes four insulated-gate field-effect transistors comprising two storage transistors both possessing the same first quotient or ratio of their channel width to their channel length. The four transistors also include two access transistors both possessing the same second quotient or ratio of their channel width to their channel length. The ratio of the first quotient to the second quotient is greater than or equal to one.

Abstract: The intrinsic collector of a vertical bipolar transitor is grown epitaxially on an extrinsic collector layer buried in a semiconductor substrate. A lateral isolation region surrounds the upper part of the intrinsic collector and an offset extrinsic collector well is produced. An SiGe heterojunction base lying above the intrinsic collector and above the lateral isolation region is produced by non-selective epitaxy. An in-situ doped emitter is produced by epitaxy on a predetermined window in the surface of the base which lies above the intrinsic collector so as to obtain, at least above the window, an emitter region formed from single-crystal silicon and directly in contact with the silicon of the base.

Abstract: A preamplifier includes an output stage having a bandwidth which is adjustable by a control signal. The output stage includes an amplifier with an adjustable bandwidth. The amplifier includes a main input for receiving an input current, a main output for providing an output voltage, a resistor connected between the main input and output. A current amplifier with an adjustable gain is connected for receiving the input current. A capacitor is connected between an output of the current amplifier and the main output. An inverting transconductance circuit is connected between the output of the current amplifier and the main output.

Abstract: An integrated circuit includes a master circuit operating at a first frequency for controlling slave circuits operating at a second frequency. The integrated circuit uses registers for eliminating difficulties arising from different and independent frequencies of the master and slave circuits.

Abstract: DC voltage levels applied to an integrated circuit are measured using an electron beam. A pulsed signal having a peak voltage dependent upon or representing one of the DC voltage level applied to the integrated circuit is first generated. The pulsed signal is applied to a test zone, and the voltage of the test zone varies according to the pulsed signal. The DC voltage level applied to the test zone on the integrated circuit transforms into a pulsed voltage. An electron beam is then used to measure the voltage of the test zone.

Abstract: A machining method is provided for use with a smart card of the type having at least one conducting winding at some distance from the opposed faces of the card, with the end portions of the winding forming electrical connection pads for an electronic chip. According to the method, an electric potential is generated in the winding. The milling tool is made to orthogonally penetrate the card in a region of at least one of the pads, and the electric potential of the milling tool is concomitantly monitored to detect a variation in electric potential that identifies a reference position of the milling tool with respect to the card and pad. The penetration of the milling tool is continued for a predetermined travel from the reference position so as to reach a machining position. In one preferred method, the milling tool is moved parallel to the card at the depth of the machining position in order to form a cavity in the smart card. A machining apparatus for machining a cavity in a smart card is also provided.

Abstract: A method of manufacturing a BICMOS integrated circuit including an NPN transistor in a heavily-doped P-type wafer coated with a lightly-doped P-type layer, including the steps of forming an N well of collector of a bipolar transistor; coating the structure with a polysilicon seed layer and opening above collector well portions; growing undoped silicon, then P-type doped silicon to form a single-crystal silicon base region; depositing an insulating layer and opening it; depositing N-type emitter polysilicon and etching it outside useful areas; etching the base silicon outside useful areas; forming spacers; and forming a collector contact area at the same time as the drain implantation of the N-channel MOS transistors.

Abstract: A delay circuit includes a primary circuit receiving an input signal and outputting two intermediate signals having a delay therebetween. A combination circuit with two modules that output a combination signal on the basis of the addition with weighting and effect of integration of the intermediate signals and of their conjugate. Each module includes a discharging circuit and a charging circuit, which each have switching elements controlling the connection between a common line and first and second supply potentials. These connections use a variable resistor and a non-variable resistor so as to ensure the permanent participation of the two modules in the charging or discharging of a capacitor. This delay circuit is particularly useful in CMOS circuits.

Abstract: The present invention relates to a circuit including at least one analog processing cell having a time constant determined by a capacitor and a resistor. A calibration circuit comprises a bridge formed of a switched-capacitance resistor and of a resistor adjustable by means of a digital control signal; and a feedback loop to adjust the digital control signal so that the voltage at the midpoint of the bridge is equal to a predetermined fraction of the voltage applied across the bridge. The resistor of the processing cell is also adjustable by the digital control signal.