Abstract: Spectrum usage in a radio cognitive transmission system may be monitored in a distributed manner in space and time through a first set of monitoring apparatuses and a second set of monitoring apparatuses. The first set of monitoring apparatuses may be associated to apparatuses, such as base stations, having a monitoring precision level, for example, linked to the spectrum sampling frequency, greater with respect to the monitoring precision of the monitoring apparatus of the second set. The later may be suitable to be represented by a low-cost “sniffer” associated to consumer electronics devices.

Abstract: An encoder allows generating, starting from a sequence of digital video pictures, a time-scalable encoded bitstream obtained by applying to the pictures, a hierarchical prediction wherein the pictures are organized in Groups Of Pictures (GOPs). The GOPs may include base time layer pictures or Key Pictures for encoding as Inter or Intra, with and without motion-compensated prediction respectively. The GOPs may also include higher time layer pictures adapted to be selectively eliminated to effect time scalability of the encoded scalable bitstream. The encoder may detect scene changes in the sequence of digital video pictures, and, in the presence of a scene change, a first Key Picture after the scene change may be encoded as Intra.

Abstract: A notch filter suitable for attenuating certain frequencies of a radio-frequency signal includes an input for receiving the radio-frequency signal and an output for the output of a portion of the radio-frequency signal, first and second capacitive means, at least one inductor and a negative resistance circuit suitable for compensating the resistive losses of said at least one inductor. The inductor and the first and second capacitive means are placed to produce a resonator and the filter comprises a control device suitable for controlling the negative resistance circuit. The input impedance of the filter comprises a pole and a zero, with the pole depending on the second capacitive means and the zero depending on both the first and second capacitive means. The first and second capacitive means are variable and the control device is suitable for controlling the first and second capacitive means.

Abstract: A method of detecting an angular position of a rotor of a motor includes detecting switching ripple peaks and armature current disturbance peaks using a peak detector configured to generate a square wave having edges coinciding with detected peaks. The method further includes filtering the square wave in a time domain by generating an integration ramp, toward a set value, of an estimated ripple frequency for an interval of time based on the estimated ripple frequency. An enablement range is established to reset the integration ramp by setting a threshold below and above the set value and a time window centered on an end time of each period of the estimated ripple frequency. The method further includes resetting the integration ramp, and updating the estimated ripple frequency based upon a period determined by a time of the resetting, if an edge of the square wave is within the time window.

Abstract: A power amplifier formed by a plurality of pairs of transistors, each pair including a first transistor and a second transistor having each a respective input terminal and a respective output terminal. The output terminals of the first and second transistors of each pair are connected to an output distributed active transformer connected to a differential output of the power amplifier. The input terminals of the first and second transistors of each pair are connected to an input distributed active transformer connected to an input of the power amplifier.

Abstract: A digital image processing system and method for removing motion effects from images of a video sequence, and generating corresponding motion compensated images.

Abstract: According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions.

Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.

Abstract: Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.

Abstract: One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.

Abstract: A non-volatile memory including a plurality of memory cells configured to store data and a plurality of redundant memory cells configured to be used for functionally replacing defective memory cells. The memory further includes a protection register comprising storage elements configured to store configuration data of the memory device. The storage elements of the protection register are redundant memory cells not being used to replace defective memory cells.

Abstract: A down-converter mixer may include a Gilbert cell, two transistor differential pairs, which drive output loads, and transistors defining respective tail generators coupled to common source nodes of the differential pairs. The transistors may receive a radio-frequency signal mixable with a local oscillator signal applied symmetrically between the differential pairs to produce in the loads, a signal deriving from down-converting the radio-frequency signal of an amount given by the frequency of the local oscillator signal. An inductor may be coupled to the common source nodes and which resonates with a capacitive load also coupled to the common source nodes, increases the impedance of such common nodes at the local oscillator signal frequency. The inductor may be in an open loop configuration in the absence of feedback from the mixer, and thus may be active both against noise at radio-frequency and distortion at low frequency.

Abstract: A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.

Abstract: A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST.

Abstract: A MEMS probe adapted to contact a corresponding terminal of an integrated circuit, integrated on at least one chip of a semiconductor material wafer during a test phase of the wafer is provided. The probe includes a support structure comprising a first access terminal and a second access terminal; the support structure defines a conductive path between said first access terminal and said second access terminal. The probes further-includes a probe region connected to the support structure adapted to contact the corresponding terminal of the integrated circuit during the test phase for providing at least one test signal received from the first access terminal and the second access terminal to the integrated circuit through at least one portion of the conductive path, and/or providing at least one test signal generated by the integrated circuit to at least one between the first access terminal and the second access terminal trough at least one portion of the conductive path.

Abstract: In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.

Abstract: The disclosure relates to an electronic differential amplification device integrated on a semiconductor chip. The device may include first and second transistors having respective source terminals connected to a first potential, and drain terminals to receive a first differential current signal. The device may include third and fourth transistors having respective source terminals connected to the first potential, and drain terminals to provide a second differential current signal to a load obtained by amplifying the first signal. The third and fourth transistors may have a respective gate terminal connected to the drain terminal of the first and the second transistors, respectively, in order to form current mirrors with the latter.

Abstract: A MEMS acoustic transducer provided with a substrate having cavity, and a membrane suspended above the cavity and fixed peripherally to the substrate, with the possibility of oscillation, through at least one membrane anchorage. The membrane comprises at least one spring arranged in the proximity of the anchorage and facing it, and is designed to act in tension or compression in a direction lying in the same plane as said membrane.

Abstract: A method of manufacturing a device for emission of optical radiation integrated on a substrate of a semiconductor material includes the steps of forming a first mirror, a second mirror of a dielectric type, and an active layer comprising a main zone designed to be excited to generate the radiation. First and second electrically conductive layers are formed and arranged to produce a generation electric signal of an electric field to which an excitation current of the main zone is associated. A dielectric region is formed between the first and the second layers by partially oxidizing the first electrically conductive layer to and thereby obtaining a thermal oxide layer, to space out corresponding peripheral portions of the first and second layers so that the electric field present in the main zone is greater than that present between the peripheral portions thus favouring a corresponding generation of the excitation current in the main zone.

Abstract: An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.