Abstract: A method for producing an integrated device including a capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate, forming a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate, forming a second conductive layer including a second plate of the capacitor and functional connections to the functional circuits on a portion of the layer of insulating material corresponding to the dielectric layer, forming a protective layer of insulating material covering the second plate and the functional connections, forming a first contact for contacting the first plate, and forming a second contact and functional contacts for contacting the second plate and the functional connections, respectively, through the protective layer.

Abstract: A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed.

Abstract: An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are connected in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor.

Abstract: An integrated power MOSFET device formed by a substrate); an epitaxial layer of N type; a sinker region of P type, extending through the epitaxial layer from the top surface and in electrical contact with the substrate; a body region, of P type, extending within the sinker region from the top surface; a source region, of N type, extending within the body region from the top surface, the source region delimiting a channel region; a gate region; a source contact, electrically connected to the body region and to the source region; a drain contact, electrically connected to the epitaxial layer; and a source metallization region, extending over the rear surface and electrically connected to the substrate and to the sinker region.

Abstract: A method of distributing media content over networks where content is shared includes coupling downloading metadata, which is accessed to start downloading media contents from the network, with semantic metadata representative of the semantic information associated with at least one of the content, and with source metadata indicative of the source of the media content. At least one of the semantic and the source metadata may be made accessible without downloading, even partially, the media content. A digital signature may also be applied to the metadata to enable the verification that, at reception, the metadata is intact and has not been subjected to malicious tampering.

Abstract: An embodiment for making a check of the electric type executed on wafer for testing the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on semiconductor wafer. An embodiment consists in making a current circulate in at least part of the seal ring of at least one of the above devices, and in case it has to flow in the seal ring of more devices, these seal rings are suitably interconnected to each other. Thanks to an embodiment the seal ring may also be reinforced in the angle areas of the chip, and suitable circuits may be possibly inserted in the seal ring or between the seal rings.

Abstract: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.

Abstract: A method is for choosing a mode out of a set of functioning modes of an integrated circuit (IC) device powered from different supply voltages from respective supply nodes. The IC device may include a mode pin for determining a functioning mode of the device, an internal control circuit coupled to the supply nodes and to the mode pin for sensing an electrical value on the mode pin and to start the IC device in a respective functioning mode depending on the supply node that is powered first. The method may include identifying the different supply voltage that first exceeds a threshold voltage, when the internal control circuit is powered, sensing the electrical value on the mode pin, and powering circuits of the IC device from the different supply voltage that first exceeded the threshold voltage and starting the device in a functioning mode determined by a value of the electrical value sensed on the mode pin and by the different supply voltage that first exceeded the voltage threshold.

Abstract: A threshold comparator with hysteresis includes a comparator circuit, having a first input, for receiving an input voltage, a second input, and an output, which supplies an output voltage having a first value and a second value. A current generator, controlled by the output voltage, supplies a current to the first input in the presence selectively of one between the first value and second value of the output voltage. A selector circuit connects the second input of the comparator circuit to a first reference voltage source, which supplies a first reference voltage, in response to first edges of the output voltage, and to a second reference voltage source, which supplies a second reference voltage, in response to second edges of the output voltage, opposite to the first edges.

Abstract: A circuit for generating a reference electrical quantity, including: a first bipolar transistor and a second bipolar transistor having the base terminals connected to one another and to a common node; a first resistor connected to the emitter terminal of the second bipolar transistor; a first mirror circuit and a second mirror circuit connected to the first and second bipolar transistors, which receive, respectively, a first current and a second current and generate, respectively, a first mirrored current and a second mirrored current; a first output stage, which generates the reference electrical quantity as a function of the first and second mirrored currents; and a second resistor connected to the common node. The first current is a function of the current in the first resistor, whilst the second current is a function of the current in the second resistor.

Abstract: A radio-frequency amplifier includes a common gate amplification stage configured to be biased in a saturation condition with a first current and configured to receive an input signal as a gate-source voltage and to generate an output voltage as an amplified replica of the input signal. A feedback transistor is configured to be biased in a saturation condition with a second current and coupled to the common gate amplification stage so as to have a gate-drain voltage corresponding to a difference between the output voltage and the input signal.

Abstract: A method is provided for controlling turn-on of phases of a multiphase regulator. According to the method, there are tested the conditions necessary for the turn-on of a phase to be turned-on indicated by a first cell of the phase register, and in response to a positive result a corresponding ramp signal is reset. There is then tested the conditions necessary for the turn-on of a phase successive to the phase to be turned on according to the list of priorities of the phase register, and corresponding ramp signals are reset if there is a positive result. In response to no positive results of testing conditions necessary for the turn-on of all phases successive to the phase to be turned on, there is reset a ramp signal corresponding to a phase successive to a last turned on phase indicated by a last cell of the phase register.

Abstract: A pulse generator circuit is provided. The pulse generator circuit has an input adapted to receive an input electrical quantity and an output at which an output electrical quantity is made available. A transfer characteristic establishes a relationship between said input and said output electrical quantities. The pulse generator circuit is adapted to provide said output electrical quantity in the form of pulses having a predetermined shape, suitable to be used for UWB transmission. The transfer characteristic has substantially a same shape as that of said pulses. Moreover, a UWB modulating system exploiting the novel pulse generator is proposed.

Abstract: A pulse generator circuit is provided. The pulse generator circuit has an input adapted to receive an input electrical quantity and an output at which an output electrical quantity is made available. A transfer characteristic establishes a relationship between said input and said output electrical quantities. The pulse generator circuit is adapted to provide said output electrical quantity in the form of pulses having a predetermined shape, suitable to be used for UWB transmission. The transfer characteristic has substantially a same shape as that of said pulses. Moreover, a UWB modulating system exploiting the novel pulse generator is proposed.

Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device connected in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal connected to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, connected between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal connected to the control terminal; and a Zener diode, connected between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.

Abstract: A charge pump having a supply terminal, for receiving a supply voltage, and an output terminal, for supplying an output voltage. The charge pump has a control block including a comparator having a first comparison input, for receiving the supply voltage, a second comparison input, for receiving the output voltage, and a comparison output, for generating a pump-switch-off signal depending upon a comparison between the input voltage and the output voltage; and a switch controlled in switching off by the pump-switch-off signal and configured for switching off the charge pump circuit. The control block has an activation input for receiving an activation signal that has a plurality of pulses and repeatedly activates the comparator-circuit block.

Abstract: A method for managing a queue, such as for example a FIFO queue, and executing a look-ahead function on the data contained in the queue includes associating to the data in the queue respective state variables (C1, C2, . . . CK), the value of each of which represents the number of times a datum is present in the queue. The look-ahead function is then executed on the respective state variables, preferentially using a number of state variables (C1, C2, . . . CK) equal to the number of different values that may be assumed by the data in the queue. The look-ahead function can involve identification of the presence of a given datum in the queue and is, in that case, executed by verifying whether among the state variables (C1, C2, . . . CK) there exists a corresponding state variable with non-nil value.

Abstract: A method of estimating log-likelihood ratios for first and second streams of samples of a received S-FSK signal demodulated using first and second carriers includes estimating channel and noise parameters associated with first and second transmitted values for the first and second streams of samples obtained from the received S-FSK modulated signal. Current signal-to-noise ratios are estimated for current samples of the first and second streams of samples obtained from the received S-FSK modulated signal using the channel and noise parameters. The estimated current signal-to-noise ratios are compared with values of a discrete ordered set and respective pairs of consecutive values of the discrete ordered set between which the estimated current signal-to-noise ratios are comprised are identified. Log-likelihood ratios are estimated for the current samples of the first and second streams.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding