Abstract: The present disclosure is directed to multichannel transducer devices and methods of operation thereof. One example device includes at least two acquisition modules that have different sensitives and a signal processing stage that generates a blended signal representative of a lower gain signal mapped onto a higher gain signal. One example method of operation includes receiving a first signal from a first sensor having a first sensitivity, receiving a second signal from a second sensor having a second sensitivity that is different from the first sensitivity, generating a blended signal by mapping the second signal to the first signal, outputting the first signal while the first signal is below a first threshold and above a second threshold, and outputting the blended signal when the first signal is above the first threshold and when the first signal is below the second threshold.

Abstract: An assembly of a MEMS sensor device envisages: a first die, integrating a micromechanical detection structure and having an external main face; a second die, integrating an electronic circuit operatively coupled to the micromechanical detection structure, electrically and mechanically coupled to the first die and having a respective external main face. Both of the external main faces of the first die and of the second die are set in direct contact with an environment external to the assembly, without interposition of a package.

Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.

Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.

Abstract: A non-volatile memory cell for storing a single bit is disclosed. The non-volatile memory cell includes an access transistor including a gate, a first body, a first source/drain node, and a second source/drain node. The non-volatile memory cell also includes a first floating gate storage transistor that has a third source/drain node, a second body, a fourth source/drain node, and a first floating gate including a first storage node. The third source/drain node is coupled to the second source/drain node. The non-volatile memory cell further includes a first capacitor, a second capacitor, and a second floating gate storage transistor. The first capacitor has a first plate coupled to the first storage node and an opposite second plate. The second floating gate storage transistor includes a fifth source/drain node, a third body, a sixth source/drain node, a second floating gate including a second storage node. The fifth source/drain node is coupled to the fourth source/drain node.

Abstract: An oscillator has an oscillator output emitting an oscillating signal. The oscillator includes oscillator cores which each have a same circuit topology. A set of configuration switches couple a selected number of oscillator cores in parallel to generate the oscillating signal. The oscillator cores are arranged with a symmetry around a central axis. The planar inductors of the oscillator cores are arranged in a petal-like pattern with the planar inductors forming the petals of the petal-like pattern. The selected coupling of the oscillator cores in made in response to a selected phase noise threshold of a modulation device which receives the oscillating signal.

Abstract: A microreactor for performing chemical reactions, includes a body, a first chamber and a second chamber, both formed in the body. Interconnections are provided for fluidly coupling the first chamber and the second chamber through the body. The microreactor also includes a venting passage formed in the body and having a venting outlet in the second chamber and at least one venting inlet in the first chamber, at a location where formation of bubbles is expected upon introduction of a liquid in the first chamber.

Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.

Abstract: An inertial sensor having a body with an excitation coil and a first sensing coil extending along a first axis. A suspended mass includes a magnetic-field concentrator, in a position corresponding to the excitation coil, and configured for displacing by inertia in a plane along the first axis. A supply and sensing circuit is electrically coupled to the excitation coil and to the first sensing coil, and is configured for generating a time-variable flow of electric current that flows in the excitation coil so as to generate a magnetic field that interacts with the magnetic-field concentrator to induce a voltage/current in the sensing coil. The integrated circuit is configured for measuring a value of the voltage/current induced in the first sensing coil so as to detect a quantity associated to the displacement of the suspended mass along the first axis.

Abstract: A motion analysis is applied to a signal to identify high-motion regions and low-motion regions. An analysis of low-level characteristics of the signal, such as a skin tone or contrast analysis, is used to generate a map of regions with low-level characteristics. The map is filtered to identify regions having both low-level characteristics and low motion. Based on a comparison of the area of the regions having both low-level characteristics and low motion to a threshold, regions of interest are identified. If the area is greater than the threshold, the regions of interest are identified as a function of the high-motion regions and of the regions that have both low-level characteristics and low motion. Otherwise, the regions of interest are identified as a function of the high-motion regions and of regions identified using face detection.

Abstract: The present disclosure is directed to a switching power converter having a power transistor controlled by a controller. The controller includes a multiplier that produces a voltage reference signal. A subtraction circuit subtracts a capacitor signal, which is based on the voltage reference signal, from a sensing signal that is representative of the current flowing through the power transistor. A comparator compares the voltage reference signal to the output of the subtraction circuit, and a driving circuit drives the power transistor based on the comparison resulting in a high power factor and low total harmonic distortion for the converter.

Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.

Abstract: An electronic device is attached to a first surface of a board which includes vias. A heat sink precursor for the electronic device is attached to the second surface of the electronic board. The heat sink precursor includes a cavity facing the vias. A wave of solder is applied to the second surface. The solder penetrates into the cavity of the heat sink precursor and flows by capillary action through the vias to join a thermal radiator and/or electronic contact of the electronic device to the vias. The solder further remains in the cavity to form a corresponding heat sink.

Abstract: A digital image having a plurality of pixels is analyzed to detect a fire condition. A first color parameter is determined from image color values of pixels of the image. A plurality of fuzzy membership functions correlated to image colors are defined, the plurality of fuzzy membership functions including a first fuzzy color membership function having a trend defined by said first color parameter. A fuzzy inference procedure is applied to pixels of the image to determine whether a fire condition is indicated by the digital image.

Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.

Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.

Abstract: Disclosed herein is an article including a garment, with a network formed on the garment. The network includes a main node with a main wired antenna, and at least one intermediate node with an intermediate wired antenna to be magnetically coupled to a respective device for that intermediate node. An electrical line electrically couples the main node to the at least one intermediate node. At least one electronic device is magnetically coupled to the intermediate wired antenna. A power supply unit is magnetically coupled to the main node via the main wired antenna thereof.

Abstract: An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.

Abstract: An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Magnetic trench structures are provided adjacent the integrated antenna.

Abstract: A system for driving a MEMS array having a number of MEMS structures, each defining at least one row terminal and one column terminal, envisages: a number of row driving stages, each for supplying row-biasing signals to the row terminal of each MEMS structure associated to a respective row; a number of column driving stages, each for supplying column-biasing signals to the column terminal of each MEMS structure associated to a respective column; and a control unit, for supplying row-address signals to the row driving stages for generation of the row-biasing signals and for supplying column-address signals to the column driving stages for generation of the column-biasing signals. The control unit further supplies row-deactivation and/or column-deactivation signals to one or more of the row and column driving stages, for causing deactivation of one or more rows and/or columns of the MEMS array.