Abstract: Described herein is an assembly of an integrated device and of a cap coupled to the integrated device; the integrated device is provided with at least a first and a second region to be fluidically accessed from outside, and the cap has an outer portion provided with at least a first and a second inlet port in fluid communication with the first and second regions. In particular, the first and second regions are arranged on a first outer face, or on respective adjacent outer faces, of the integrated device, and an interface structure is set between the integrated device and the outer portion of the cap, and is provided with a channel arrangement for routing the first and second regions towards the first and second inlets.

Abstract: An integrated amplifier may include a transconductance stage including a differential pair of input transistors of a first type of conductivity, respective resistive loads coupled to said input transistors, and a first bias circuit coupled to the input transistors. The first bias circuit may include a second differential pair of bias transistors having first conduction terminals coupled in common and second conduction terminals coupled to respective conduction terminals of the input transistors. The first bias circuit may also include respective second bias circuits coupled to the bias transistors to enable the input transistors in a conduction state with the input transistors being biased by a same respective bias current that flows through the respective input transistors. The first bias circuit may also include a capacitive network coupled to the bias transistors to define with the input transistors a feedback loop.

Abstract: A process for forming a dielectric isolation structure on a silicon substrate includes forming at least one trench in the substrate, performing a high-temperature treatment in an oxidizing environment to form a first liner layer of silicon dioxide on the walls and the bottom of the trench, and performing a silicon dioxide deposition treatment to form a second liner layer on the first liner layer. A silicon nitride deposition treatment is also performed to form a third liner layer on the second liner layer. The trench is filled with isolating material.

Abstract: A method of managing a multi-level memory device having singularly addressable three-level cells includes storing strings of three bits by coding them in corresponding ternary strings according to a coding scheme and writing each of the ternary strings in a respective pair of three-level cells. Strings of three bits are read by reading respective ternary strings written in respective pairs of three-level cells and decoding each read ternary string in a corresponding string of three bits according to the coding scheme. A pair of adjacent bits, belonging to at least one of a same initial string and two initial adjacent strings, are programmed by identifying pairs of three-level cells to be programmed that encode the strings of three bits and programming each pair of three-level cells.

Abstract: A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, each electrode including a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer; and forming a plurality of electrodes of transistors of the circuitry each including a first dielectric layer and a first conductive layer. The method also includes forming first coating spacers on the side walls of the gate electrodes of the memory cell and second coating spacers on the side walls of the gate electrodes of the circuitry, the second spacers being wider than the first spacers.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: A voltage regulator having an input terminal for receiving an input voltage and an output terminal for providing a regulated voltage, the voltage regulator including: a differential amplifier configured for receiving a reference voltage and a feedback signal being a function of the regulated voltage, and for providing a regulation signal according to a comparison between the reference voltage and the feedback signal, a regulation transistor having a control terminal for receiving the regulation signal, a first terminal for receiving the first voltage and a second terminal coupled with the output terminal of the voltage regulator, wherein a voltage-controlled circuit coupled to the output terminal, responsive to a voltage difference between the first voltage and the regulation voltage and adapted to sink from the output terminal a current depending on said voltage difference between the supply voltage and the regulation voltage, said current being related to a leakage current of the regulation transistor.

Abstract: A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one having a reference threshold voltage, means for detecting the reaching of a comparison current by a cell current of each memory cell and by a reference current of each reference cell, and means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and the reference currents, and writing means for applying a writing voltage to at least one selected of the memory cells; the refresh circuit further includes control means for enabling the writing means during at least part of the application of the biasing voltage after the determination of the condition of each selected memory cell.

Abstract: An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain region formed in the semiconductor material layer. The source and drain regions are spaced apart from each other by a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, the insulated gate extending over the charge carriers drift portion. The drain region is located at a depth compared to the front surface for causing charge carriers to move in the charge carriers drift portion away from an interface between the semiconductor material layer and the gate dielectric.

Abstract: A multi-standard transmitter includes a differential stage that includes a current generator transistor; first and second transistors connected between a first node and the generator transistor and having respective control terminals connected to a first input terminal, the first and second transistors being interconnected at a first output terminal; third and fourth transistors connected between the first node and the generator transistor and having respective control terminals connected to a second input terminal, the third and fourth transistors being interconnected at a second output terminal; and first and second resistances connected between the first and second output terminals and interconnected at a second node. The transmitter includes a selective enabling circuit connected to the first and second nodes, and to a third node corresponding to a control terminal of the generator transistor.

Abstract: A process for manufacturing a through via in a semiconductor device includes the steps of: forming a body having a structural layer, a substrate, and a dielectric layer set between the structural layer and the substrate; insulating a portion of the structural layer to form a front-side interconnection region; insulating a portion of the substrate to form a back-side interconnection region; and connecting the front-side interconnection region and the back-side interconnection region through the dielectric layer.

Abstract: A demodulator includes input terminals, for receiving an input signal, and an amplifier stage having a gain. The input signal is amplitude-modulated and is defined by a carrier signal at a carrier frequency and by a modulating signal. The demodulator includes, moreover, a gain-control stage, coupled to the amplifier stage for varying the gain of the amplifier stage according to a sinusoid of a frequency equal to the carrier frequency, on the basis of the carrier signal.

Abstract: An embodiment of a control circuit is proposed for turning on a power switching device, the switching device turning on in response to a control signal exceeding a threshold value. The control circuit includes pre-charging means for providing the control signal at a pre-charging value not reaching the threshold value, and soft turn-on means for gradually increasing the control signal from the pre-charging value to a turn-on value exceeding the threshold value; the pre-charging means includes means for sensing an indication of the threshold value, and means for setting the pre-charging value according to the sensed threshold value.

Abstract: An architecture for implementing an integrated capacity includes a capacitive block inserted between first and second voltage reference. The block is formed The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block.

Abstract: A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

Abstract: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.

Abstract: A multisense-adaptive reading circuit is described, which is associated to a sense element of an interleaved DC-DC converter module. The reading circuit comprises at least a first and second current source connected to a first and second terminal of the module, connected in turn to a first and second resistive element, as well as a tracker of a current information coming from the first and second current source. Advantageously according to the invention, the reading circuit also comprises a reading mode detector effective to detect a common mode voltage value and, based on this value, to determine a reading mode being used among possible reading modes to self-adapt the reading circuit to the reading mode being used by providing convenient enabling signals to the first and second current sources and to the tracker. A multisense-self-adaptive reading method being implemented by means of that circuit is also described.

Abstract: A method for sealing electronic devices formed on a semiconductor substrate includes forming a plurality of first electronic devices adjacent a first portion of the semiconductor substrate, with each first electronic device including a first region comprising at least one first conductive layer projecting from the semiconductor substrate. A first sealing layer is formed adjacent the first regions for sealing the plurality of first electronic devices. A protective layer is formed adjacent the first sealing layer. The protective layer is etched to form protective spacers adjacent sidewalls of the first regions. The method further includes forming a plurality of second electronic devices adjacent a second portion of the semiconductor substrate, with each second electronic device including a second region comprising a second conductive layer projecting from the semiconductor substrate.

Abstract: A circuit matches the load impedance of an electronic device. The circuit comprises an impedance network, a control circuit suitable for varying the impedance of said network and a sensor coupled with said network and said load and suitable for detecting the ratio between the incident and reflected standing waves in transferring power from the electronic device to the load; the sensor is suitable for providing two signals substantially proportional to the incident and reflected amplitude of the waves at the control circuit. The impedance network is a network of variable resistances and the control circuit is suitable for varying the value of the resistances to lower said ratio between the incident and reflected standing waves to a value that ensures the transfer of power from the electronic device to the load.

Abstract: A protection device protects a driving device of an electric motor with at least three phases and at least three windings and the driving device comprises a power stage suitable for driving directly said at least three windings. The driving device is suitable for actuating a motor brake operating phase and comprises detectors suitable for detecting the currents that run in the windings of the motor. The protection device comprises selectors suitable for selecting the currents having a single direction between said detected currents and a deactuator suitable for deactuating the power stage during said motor brake operating phase when the sum of the currents having a single direction is greater than a reference current.