Abstract: Various embodiments of the present disclosure provide a read/write device for a hard-disk memory system. The read/write device includes a fixed structure; a membrane region including a first and a second membrane, which are constrained to the fixed structure, and a central portion, interposed between the first and second membranes; a first and a second piezoelectric actuator, mechanically coupled, respectively, to the first and second membranes; and a read/write head, which is fixed to the central portion of the membrane region. The first and second piezoelectric actuators can be controlled so as to cause corresponding deformations of the first and second membranes, said deformations of the first and second membranes causing corresponding movements of the read/write head with respect to the fixed structure.

Abstract: One or more keys are derived from a master key by executing a plurality of encryption operations. A first encryption operation uses the master key to encrypt a plaintext input having a plurality of bytes. Multiple intermediate encryption operations are performed using a respective intermediate key generated by a previous encryption operation to encrypt respective plaintext inputs having a number of bytes. At least two bytes of a plaintext input have values based on a respective set of bits of a plurality of sets of bits of an initialization vector, wherein individual bits of the respective set of bits are introduced into respective individual bytes of the plaintext input and the respective set of bits has at least two bits and at most a number of bits equal to the number of bytes of the plaintext input.

Abstract: A control circuit for a driving an electronic switch associated with a switching node of a flyback converter includes a comparison circuit configured to generate a switch-off signal by comparing a current measurement signal with a current measurement threshold signal. A valley detection circuit is configured to generate a trigger in a trigger signal when a valley signal indicates a valley in a voltage at the switching node of the flyback converter, and a blanking circuit is configured to generate a switch-on signal by combining the trigger signal with a timer signal provide by a timer circuit. The timer signal indicates whether a blanking time-interval has elapsed.

Abstract: A first node of converter circuit receives an input, provides an output at a second node, and has a third node coupled by an inductance to ground. A first switch has a current path between the first and third nodes and a second switch has a current path between the third and second nodes. The converter circuit operates in a first state (with the first switch conductive and the second switch non-conductive) and a second state (with the first switch non-conductive and the second switch conductive). Current flowing through the first switch is sensed during the first state to produce a sensing signal indicative of inductance current. The sensing signal is averaged to produce an averaged sensing signal indicative of an average value of the current. The averaged sensing signal is then weighted by a time during which the second switch is conductive to produce a weighted signal.

Abstract: A microfluidic valve formed in a body having a first and a second surface; an inlet channel extending in the body from the second surface; a first transverse channel extending in the body in a transverse direction with respect to the inlet channel; and an outlet channel extending in the body from the first surface. The inlet channel, the first transverse channel and the outlet channel form a fluidic path. The microfluidic valve further has an occluding portion, formed by the body and extending over the transverse channel; and a piezoelectric actuator coupled to the occluding portion and configured to move the occluding portion from an opening position of the valve, where the occluding portion does not interfere with the fluidic path, and a closing position of the valve, where the occluding portion interferes with and interrupts the fluidic path.

Abstract: A leadframe for semiconductor devices, the leadframe comprising a die pad portion having a first planar die-mounting surface and a second planar surface opposed the first surface, the first surface and the second surface having facing peripheral rims jointly defining a peripheral outline of the die pad wherein the die pad comprises at least one package molding compound receiving cavity opening at the periphery of said first planar surface.

Abstract: A circuit includes comparator circuitry to sense a current through a load and compare the intensity of the current with a comparison threshold which can be set to a first, lower threshold value and a second, higher threshold value. Logic circuitry receives from the comparator circuitry a comparison signal having a first value or a second value based on whether the intensity is lower or higher than the comparison threshold. The logic circuitry is configured to assert a first overcurrent event signal or a second overcurrent event signal based on the comparison signal having the first value or the second value and the comparison threshold set to the first or second threshold value.

Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.

Abstract: A light projection system includes a microelectromechanical (MEMS) mirror configured to operate in response to a mirror drive signal and to generate a mirror sense signal as a result of the operation. A mirror driver is configured to generate the mirror drive signal in response to a drive control signal. A zero cross detector is configured to detect zero crosses of the mirror sense signal. A controller is configured to generate the drive control signal as a function of the detected zero crosses of the mirror sense signal.

Abstract: System for detecting a touch gesture of a user on a detection surface, comprising: a processing unit; and an accelerometer to detect a vibration at the detection surface and generate a vibration signal. The processing unit is configured to: acquire the vibration signal, detect, in the vibration signal, a signal characteristic which can be correlated to the touch gesture of the user, detect, in the vibration signal, a stationarity condition preceding and/or following the detected signal characteristic, and validate the touch gesture in the event that both the signal characteristic and the stationarity condition have been detected. An electrostatic charge sensor may also be used as a further parameter to validate the touch gesture.

Abstract: Various embodiments of the present disclosure provide a power device including at least one first conductive element adapted to generate a magnetic field when traversed by a current, and characterised in that it further comprises a Hall sensor electrically insulated from the first conductive element. The sensor and the first conductive element are mutually arranged so as to detect said magnetic field indicative of the current that traverses the first conductive element.

Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.

Abstract: An integrated circuit (IC) includes: an input terminal; an output terminal; a first reference voltage terminal and a second reference voltage terminal; a high-side power switch coupled between the first reference voltage terminal and the output terminal; a low-side power switch coupled between the output terminal and the second reference voltage terminal; a first combinational logic and a second combination logic that are coupled to the input terminal; a first driver coupled between the first combinational logic and the high-side power switch; a second driver coupled between the second combinational logic and the low-side power switch; and first comparators coupled to the second combinational logic, where the first comparators are configured to compare a voltage difference between load path terminals of the high-side power switch with a first threshold and a second threshold.

Abstract: In an embodiment, a method for operating an ACF converter includes: turning on a low-side transistor that is coupled between a primary winding of a transformer and a reference terminal to cause a forward current to enter the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor that is coupled between the primary winding and a clamp capacitor to cause a reverse current to flow through the primary winding; and after turning on the high-side transistor, when an overcurrent of the reverse current is not detected, keeping the high-side transistor on for a first period of time, and turning off the high-side transistor after the first period of time, and when the overcurrent of the reverse current is detected, turning off the high-side transistor without keeping the high-side transistor on for the first period of time.

Abstract: Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.

Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/out register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/out register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event.

Abstract: A semiconductor chip is arranged over a substrate in the form of a leadframe. A set of current-carrying formations configured as conductive ribbons are coupled to the semiconductor chip. The substrate does not include electrically conductive formations for electrically coupling the conductive ribbons to each other. Electrical contacts are formed via wedge bonding, for instance, between adjacent ones of the conductive ribbons so that a contact is provided between the adjacent ones of the conductive ribbons in support of a multi-formation current-carrying channel.

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.