Abstract: The present disclosure relates to solutions for operating a flyback converter comprising an active clamp. The flyback converter comprises two input terminals and two output terminals. A first electronic switch and the primary winding of a transformer are connected in series between the input terminals. An active clamp circuit is connected in parallel with the primary winding. The active clamp circuit comprises a series connection of a clamp capacitor and a second electronic switch. A third electronic switch and the secondary winding of the transformer are connected in series between the two output terminals. In particular, the present disclosure relates to solutions for switching the first, second and third electronic switch in order to achieve a zero-voltage switching of the first electronic switch.

Abstract: A device has memory and processing circuitry coupled to the memory. The processing circuitry generates a resonant axis drive signal to drive a Micro Electro Mechanical System (MEMS) mirror system at a resonance frequency, and generates a linear axis drive signal to drive the MEMS mirror system at a linear frequency corresponding to a video frame rate. Generating the linear axis drive signal includes generating, using interpolation, a current set of shape values based on a stored set of shape values and an indication of the video frame rate. The linear axis drive signal is generated using the current set of shape values.

Abstract: In an embodiment, a device comprises a memory, which, in operation, stores data samples associated with a plurality of data sensors, and circuitry, coupled to the memory, wherein the circuitry, in operation, generates synchronized output data sets associated with the plurality of data sensors. Generating a synchronized output data set includes: determining a reference sample associated with a sensor of the plurality of sensors; verifying a timing validity of a data sample associated with another sensor of the plurality of sensors; identifying a closest-in-time data sample associated with the another sensor of the plurality of sensors with respect to the reference sample; and generating the synchronized output data set based on interpolation.

Abstract: A circuit includes processing circuitry is sensitive to a regulated voltage at the output node and to a temperature of the circuit. The processing circuit is configured to provide voltage and temperature sensing signals indicative of the regulated voltage at the output node and the temperature of the circuit. The processing circuitry is configured to assume i) a first state, as a result of the voltage sensing signal reaching a voltage threshold, ii) a second state, as a result of the temperature detection signal reaching a temperature threshold, or iii) a third state, as a result of both the voltage and the temperature sensing signals failing to reach the thresholds. The circuit comprises a warning output coupled to a warning signal generation network controlled by the processing circuitry.

Abstract: An apparatus includes a digital-to-analog converter coupled in series with a source follower, wherein the digital-to-analog converter is configured to control a current flowing through the source follower, and an amplifier having a first input coupled to a reference generator, a second input coupled to a common node of the source follower and the digital-to-analog converter, and an output coupled to a gate of the source follower.

Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

Abstract: A microelectromechanical membrane transducer includes: a supporting structure; a cavity formed in the supporting structure; a membrane coupled to the supporting structure so as to cover the cavity on one side; a cantilever damper, which is fixed to the supporting structure around the perimeter of the membrane and extends towards the inside of the membrane at a distance from the membrane; and a damper piezoelectric actuator set on the cantilever damper and configured so as to bend the cantilever damper towards the membrane in response to an electrical actuation signal.

Abstract: A planar Hall sensing element includes a first pair of sensing electrodes mutually opposed in a first direction across the sensing element and a second pair of sensing electrodes mutually opposed in a second direction across the sensing element, with the second direction orthogonal to the first direction. A first pair of bias electrodes is mutually opposed in a third direction and a second pair mutually opposed in a fourth direction across the sensing element, the fourth direction orthogonal to the third direction. The third and fourth directions are rotated 45° with respect to the first and second directions so each sensing electrode is arranged between a bias electrode of the first pair and second pair. A DC bias current is supplied between the first and second pairs of bias electrodes. First and second Hall voltages are sensed at the first and second pairs of sensing electrodes.

Abstract: A device for detecting UV radiation, comprising: a SiC substrate having an N doping; a SiC drift layer having an N doping, which extends over the substrate; a cathode terminal; and an anode terminal. The anode terminal comprises: a doped anode region having a P doping, which extends in the drift layer; and an ohmic-contact region including one or more carbon-rich layers, in particular graphene and/or graphite layers, which extends in the doped anode region. The ohmic-contact region is transparent to the UV radiation to be detected.

Abstract: An analysis unit formed by an analysis body housing an analysis chamber and having a sample inlet and a supply channel configured to fluidically connect the sample inlet to the analysis chamber. Dried assay reagents are arranged in the analysis chamber and are contained in an alveolar mass. For instance, the alveolar mass is a lyophilized mass formed by excipients and by assay-specific reagents.

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

Abstract: A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A converter includes two switching stages coupled in series between positive and negative input terminals. A control circuit is configured for driving the switching stages based on an output voltage of the converter. A first switching stage includes two switches coupled in series between a positive input terminal and a first node. A capacitor and an inductor are coupled in series between the two switches and a positive output terminal. A third switch is coupled between a node between the capacitor and the inductor and the negative input terminal. A second capacitor is coupled between the first node and the negative input terminal. A second switching stage includes a second node coupled to the first node. Two additional electronic switches are coupled in series between the second node and the negative input terminal. A second inductor is coupled between the two additional switches and the positive output terminal.

Abstract: An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

Abstract: A control circuit for controlling switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse-width modulated (PWM) signal in response to a phase comparison of two clock signals. A first clock signal has a frequency determined as a function of a first feedback signal proportional to converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal, and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to a derivative of the converter output voltage. A delay line introduces a delay in the first clock signal that is dependent on the first and second currents as well as a compensation current dependent on a selected operational mode of the converter.

Abstract: A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.

Abstract: A method of operating a radar sensor system includes: frequency down-converting a reception signal that is chirp-modulated with a sequence of chirp ramps to an intermediate frequency signal; and high-pass filtering the intermediate frequency signal to produce a high-pass filtered signal. High-pass filtering includes: first high-pass filtering, with a first corner frequency, the intermediate frequency signal at each chirp in the chirp modulation of the reception signal; and replacing the first high-pass filtering with a second high-pass filtering with a second corner frequency, the first corner frequency being higher than the second corner frequency.

Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.