Patents Assigned to STMicroelectronics S.r.l.
  • Electronic circuit for tripling frequency
    Patent number: 11271552
    Abstract: In an embodiment, a circuit for tripling frequency is configured to receive an input voltage (Vin) having a sinusoidal shape and a base frequency. The circuit has a first and a second transistor pair that are cross-coupled, and a trans-characteristics f(Vin) approximating a polynomial nominal trans-characteristic given by f ? ( V in ) = ( 3 A ? V in - 4 A 3 ? V in 3 ) ? g m where A represents an amplitude of the input voltage and gm is a transconductance of transistors of the first and second transistor pairs.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: March 8, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mahmoud Mahdipour Pirbazari, Andrea Mazzanti, Andrea Pallotta
  • LED driver circuit, corresponding device and method
    Patent number: 11271555
    Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns, an oscillator configured to generate a clock signal for the FSM, a first signal path activatable between the first slave address pin and the FSM, and a second signal path activatable between the FSM and the second slave address pin.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 8, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ignazio Cala', Santi Carlo Adamo
  • METHOD OF PRODUCING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE
    Publication number: 20220068788
    Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 3, 2022
    Applicants: STMicroelectronics S.r.l., STMicroelectronics SDN BHD
    Inventors: Andrea ALBERTINETTI, Marifi Corregidor CAGUD
  • MEMORY DEVICE
    Publication number: 20220068395
    Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.
    Type: Application
    Filed: August 20, 2021
    Publication date: March 3, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Marcella CARISSIMI, Fabio Enrico Carlo DISEGNI, Chantal AURICCHIO, Cesare TORTI, Davide MANFRE', Laura CAPECCHI, Emanuela CALVETTI, Stefano ZANCHI
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE
    Publication number: 20220068741
    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 3, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Pierangelo MAGNI, Michele DERAI
  • ELECTRONIC DEVICE AND CORRESPONDING SELF-TEST METHOD
    Publication number: 20220065923
    Abstract: An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.
    Type: Application
    Filed: August 19, 2021
    Publication date: March 3, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mirko DONDINI, Roberto CRISAFULLI, Calogero Andrea TRECARICHI, Vincenzo RANDAZZO
  • High voltage driving electronic circuit arrangement having a short circuit protection, corresponding apparatus and method
    Patent number: 11264982
    Abstract: A high voltage driving circuit for driving a load receives a low voltage input signal and generates a high voltage output signal. A short circuit protection circuit including a first electronic switch operated by the low voltage input signal and a second electronic switch operated by a low voltage signal obtained by a voltage division of the output high voltage signal. The first electronic switch causing a first pull-up current to be sent to a capacitive element whose voltage controls an input of a threshold comparator. A second electronic switch causes a second pull-down current to be drawn from the capacitive element whose voltage controls the input of the threshold comparator. A short circuit detection signal is generated at an output of said threshold comparator, indicating a short circuit and capable of inhibiting operation of the driving circuit.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 1, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Terenzi, Davide Ugo Ghisu
  • Method, circuit, and apparatus to increase robustness to inrush current in power switch devices
    Patent number: 11264893
    Abstract: In accordance with an embodiment, a method includes receiving an enable signal. After the enable signal is asserted, it is determined whether a soft-start capacitor is electrically connected to an input of a ramp generator circuit while keeping an output of the ramp generator circuit low. If the soft-start capacitor is electrically connected to the input of the ramp generator circuit, a first current is injected into the input of the ramp generator circuit to generate a first voltage ramp at the output of the ramp generator circuit. If the soft-start capacitor is not electrically connected to the input of the ramp generator circuit, a second current is injected to the input of the ramp generator circuit to generate a second voltage ramp at the output of the ramp generator circuit. The second current is smaller than the first current.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 1, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventor: Marco Martini
  • Managing memory sector swapping using write transaction counts
    Patent number: 11263125
    Abstract: A method can be used for managing a memory circuit that includes memory sectors having respective positions in the memory circuit as well as respective addresses for data transfer transactions. The method includes maintaining a record of coupling pairs of the positions and the addresses. Each coupling pair includes a memory sector in the plurality of memory sectors and an address coupled with the memory sector for data transfer transactions with respect to the memory sector. The method also includes keeping counts of the data transfer transactions involving the memory sectors in the plurality of memory sectors and replacing a first memory sector included in a coupling pair and having a first count of transactions with a second memory sector having a second count of transactions as a result of a condition being met.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 1, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Alberto Saviotti
  • Analog-to-digital converter circuit, corresponding device and method
    Patent number: 11265004
    Abstract: In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 1, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giuseppe D'Angelo
  • Fluid ejection device with reduced number of components, and method for manufacturing the fluid ejection device
    Patent number: 11260659
    Abstract: Various embodiments provide an ejection device for a fluid. The ejection device includes a first semiconductor wafer, housing, on a first side thereof, a piezoelectric actuator and an outlet channel for the fluid alongside the piezoelectric actuator; a second semiconductor wafer having, on a first side thereof, a recess and, on a second side thereof opposite to the first side, at least one inlet channel for said fluid fluidically coupled to the recess; and a dry-film coupled to a second side, opposite to the first side, of the first wafer. The first and the second wafers are coupled together so that the piezoelectric actuator and the outlet channel are set directly facing, and completely contained in, the recess that forms a reservoir for the fluid. The dry-film has an ejection nozzle.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: March 1, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Domenico Giusti, Carlo Luigi Prelini, Lorenzo Tentori
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, AND CORRESPONDING TOOL
    Publication number: 20220059369
    Abstract: A semiconductor die is attached to a die pad of a leadframe. The semiconductor die attached to the die pad is arranged in a molding cavity between complementary first and second mold portions. Package material is injected into the molding cavity via at least one injection channel provided in one of the complementary first and second mold portions. Air is evacuated from the molding cavity via at least one air venting channel provided in the other of the complementary first and second mold portions. An exit from the at least one air venting channel may be blocked by a retractable stopper during the injection of the package material.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 24, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Marco ROVITTO, Pierangelo MAGNI, Fabio MARCHISI
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE
    Publication number: 20220059368
    Abstract: At least one semiconductor chip or die is held within at a chip retaining formation provided in a chip holding device. The chip holding device is then positioned with the at least one semiconductor chip or die arranged facing a chip attachment location in a chip mounting substrate. This positioning produces a cavity between the at least one semiconductor chip or die arranged at the chip retaining formation and the chip attachment location in the chip mounting substrate. A chip attachment material is dispensed into the cavity. Once cured, the chip attachment material attaches the at least one semiconductor chip or die onto the substrate at the chip attachment location in the chip mounting substrate.
    Type: Application
    Filed: August 10, 2021
    Publication date: February 24, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Fulvio Vittorio FONTANA, Marco ROVITTO
  • Voltage-current converter, corresponding device and method
    Patent number: 11256280
    Abstract: An embodiment voltage-current converter circuit comprises a first amplifier and a second amplifier having homologous first input nodes configured to receive a voltage signal therebetween as well as homologous second input nodes having a resistor coupled therebetween. First and second current mirror circuits are provided comprising first input transistors having their control terminal coupled to the output nodes of the amplifiers. First and second current sensing circuitry having first and second current output nodes are coupled to the current mirror output nodes of the current mirror circuits and configured to provide therebetween a current which is a function of the voltage signal between the homologous first input nodes of the amplifier.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 22, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Roberto Pio Baorda, Paolo Angelini
  • Photovoltaic cell
    Patent number: 11257975
    Abstract: A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: February 22, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cosimo Gerardi, Cristina Tringali, Sebastiano Ravesi, Marina Foti, NoemiGraziana Sparta', Corrado Accardi, Stella Loverso
  • Pressure sensor encapsulated in elastomeric material, and system including the pressure sensor
    Patent number: 11254561
    Abstract: A packaged pressure sensor, comprising: a MEMS pressure-sensor chip; and an encapsulating layer of elastomeric material, in particular PDMS, which extends over the MEMS pressure-sensor chip and forms a means for transferring a force, applied on a surface thereof, towards the MEMS pressure-sensor chip.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: February 22, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Enri Duqi, Bruno Murari, Sebastiano Conti
  • Real-time update method for a differential memory, differential memory and electronic system
    Patent number: 11256442
    Abstract: A method for operating a differential memory includes: operating a main memory module differentially while executing a first program; copying first logic data from a first submodule of the main memory module to an auxiliary memory module; storing third logic data associated with a second program in a second submodule of the main memory module by overwriting second logic data associated with the first program, while maintaining the first logic data contained in the first submodule of the main memory module unaltered, where the second logic data are complementary to the first logic data; when a request for reading the first logic data is received during the storing of the third logic data in the second submodule of the main memory module, reading the first logic data from the auxiliary memory module; and executing the first or second programs by operating the main memory module in single-ended mode.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: February 22, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventor: Fabio Enrico Carlo Disegni
  • PFC control circuit for a boost converter, related integrated circuit, boost converter, power supply and method
    Patent number: 11258354
    Abstract: An embodiment PFC control circuit includes a first terminal providing a drive signal to an electronic switch of a boost converter, a second terminal receiving a feedback signal indicative of an output voltage generated by the boost converter, and a third terminal connected to a compensation network. An error amplifier generates a current as a function of the voltage at the second terminal and a reference voltage, wherein an output of the error amplifier is coupled to the third terminal. A driver circuit generates the drive signal as a function of the voltage at the third terminal, and selectively activates or deactivates the generation of the drive signal as a function of a burst mode enable signal. A detection circuit generates the burst mode enable signal as a function of the voltage at the second terminal.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: February 22, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alfio Pasqua, Salvatore Tumminaro, Marco Sammartano, Claudio Adragna
  • PWM SIGNAL GENERATOR CIRCUIT AND RELATED INTEGRATED CIRCUIT
    Publication number: 20220052672
    Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Domenico TRIPODI, Luca GIUSSANI, Simone Ludwig DALLA STELLA
  • MOSFET device with shielding region and manufacturing method thereof
    Patent number: 11251296
    Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Edoardo Zanetti