Patents Assigned to STMicroelectronics S.r.l.
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Patent number: 11249562Abstract: In an embodiment pointing electronic device, a sensor fusion processing stage generates an orientation estimation quantity indicative of an orientation about a longitudinal axis based on a sensor fusion algorithm envisaging processing of acceleration and gyroscopic signals; and a pointing determination stage implements an orientation-compensation of the gyroscopic signal as a function of the orientation estimation and generates screen-frame displacement data corresponding to 3D-space movements of the pointing electronic device based on the orientation-compensated gyroscopic signal.Type: GrantFiled: January 29, 2021Date of Patent: February 15, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Federico Rizzardini, Stefano Paolo Rivolta, Lorenzo Bracco
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Patent number: 11250808Abstract: A display system comprises a processing circuit configured to receive image data from a video source, and generate a current image frame by generating pixel data as a function of the image data and storing the pixel data to a frame buffer. A graphic video driver is configured to display the image frame by reading the pixel data from the frame buffer and generating drive signals for the graphic display as a function of the pixel data read. The processing circuit also is configured to insert integrity data into the pixel data of the current image frame, wherein the position of the integrity data within the pixel data changes. The display system comprises a further processing circuit configured to read the pixel data from the frame buffer and verify whether the position of the integrity data within the pixel data changes.Type: GrantFiled: April 24, 2020Date of Patent: February 15, 2022Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (GRAND OUEST) SASInventors: Alessandro Vittorio Galluzzi, Mustapha Ghanmi
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Patent number: 11251754Abstract: A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.Type: GrantFiled: February 19, 2020Date of Patent: February 15, 2022Assignee: STMicroelectronics S.r.l.Inventors: Noemi Gallo, Edoardo Botti
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Patent number: 11251580Abstract: An integrated optical device, including: a semiconductor body delimited by a top surface; and at least one buried cavity, which extends in the semiconductor body, at a distance from the top surface, so as to delimit at the bottom a front semiconductor region, which functions as an optical guide.Type: GrantFiled: October 30, 2019Date of Patent: February 15, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Flavio Francesco Villa, Guido Chiaretti, Gabriele Barlocchi
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Publication number: 20220043136Abstract: A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.Type: ApplicationFiled: August 5, 2021Publication date: February 10, 2022Applicant: STMicroelectronics S.r.l.Inventors: Alessandro FINOCCHIARO, Alessandro PARISI, Andrea CAVARRA, Giuseppe PAPOTTO, Giuseppe PALMISANO
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Publication number: 20220045608Abstract: A converter circuit includes first and second electronic switches coupled at an intermediate node, with an inductor coupled between the intermediate node and an output node. Switching drive control circuitry causes the first and the second electronic switch to switch between a conductive state and a non-conductive state. The drive control circuitry includes a first feedback signal path to control switching of the first and the second electronic switch as a function of the difference between a feedback signal indicative of the signal at the output node and a reference value. A second feedback signal path includes a low-pass filter coupled to the output node and configured to provide a low-pass filtered feedback signal resulting from low-pass filtering of the output signal. The second feedback signal path compensates the feedback signal as a function of the difference between the low-pass filtered feedback signal and a respective reference value.Type: ApplicationFiled: August 3, 2021Publication date: February 10, 2022Applicant: STMicroelectronics S.r.l.Inventors: Alessandro BERTOLINI, Alberto CATTANI, Stefano RAMORINI, Alessandro GASPARINI
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Publication number: 20220043137Abstract: An oscillator includes a tunable resonant circuit having an inductance and a variable capacitance coupled between first and second nodes, and a set of capacitances selectively coupleable between the first and second nodes. An input control node receiving an input control signal is coupled to the variable capacitance and set of capacitances. The tunable resonant circuit is tunable based on the input control signal. A biasing circuit biases the tunable resonant circuit to generate a variable-frequency output signal between the first and second nodes. A voltage divider generates a set of different voltage thresholds, and a set of comparator circuits with hysteresis compares the input control signal to the set of different voltage thresholds to generate a set of control signals. The capacitances in the set of capacitances are selectively coupleable between the first and second nodes as a function of control signals in the set of control signals.Type: ApplicationFiled: August 5, 2021Publication date: February 10, 2022Applicant: STMicroelectronics S.r.l.Inventors: Alessandro PARISI, Andrea CAVARRA, Alessandro FINOCCHIARO, Giuseppe PAPOTTO, Giuseppe PALMISANO
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Publication number: 20220041429Abstract: A microelectromechanical sensor device has a detection structure including: a substrate having a first surface; a mobile structure having an inertial mass suspended above the substrate at a first area of the first surface so as to perform at least one inertial movement with respect to the substrate; and a fixed structure having fixed electrodes suspended above the substrate at the first area and defining with the mobile structure a capacitive coupling to form at least one sensing capacitor. The device further includes a single monolithic mechanical-anchorage structure positioned at a second area of the first surface separate from the first area and coupled to the mobile structure, the fixed structure, and the substrate and connection elements that couple the mobile structure and the fixed structure mechanically to the single mechanical-anchorage structure.Type: ApplicationFiled: July 23, 2021Publication date: February 10, 2022Applicant: STMICROELECTRONICS S.R.L.Inventors: Francesco RIZZINI, Carlo VALZASINA, Gabriele GATTERE
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Patent number: 11242242Abstract: A microfluidic MEMS device is formed by a plurality of ejection cells each having a fluid chamber; an actuator chamber; a membrane having a first surface facing the actuator chamber and a second surface facing the fluid chamber; a piezoelectric actuator on the first surface of the membrane; and a passivation layer on the piezoelectric actuator. The membrane has an elongated area defining a longitudinal direction and a transverse direction. The passivation layer has a plurality of holes. The holes extend throughout the thickness of the passivation layer and, in a plan view, have an elongated shape with a greater dimension parallel to the longitudinal direction of the membrane and a smaller dimension parallel to the transverse direction.Type: GrantFiled: May 24, 2019Date of Patent: February 8, 2022Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS, INC.Inventors: Domenico Giusti, Simon Dodd
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Patent number: 11243299Abstract: A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer.Type: GrantFiled: March 5, 2020Date of Patent: February 8, 2022Assignee: STMicroelectronics S.r.l.Inventors: Marco Passoni, Niccolò Petrini
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Patent number: 11245369Abstract: An integrated circuit includes a die that includes a circuit configured to generate a PWM signal in response to a first clock signal, and a first set of pads configured to provide amplified PWM signals to external filters. An amplifier stage is configured to provide the amplified PWM signals. The die includes two pads configured to be coupled to an external inductor, and a second set of pads configured to provide regulated voltages. An electronic converter circuit is configured to generate the regulated voltages to supply the amplifier stage. The electronic converter circuit includes a control circuit configured to drive electronic switches in response to a second clock signal to regulate the regulated voltages to a respective target value. The die includes a control block to synchronize the switching activity of the electronic switches with the switching activity of the amplifier stage.Type: GrantFiled: July 22, 2020Date of Patent: February 8, 2022Assignee: STMicroelectronics S.r.l.Inventors: Edoardo Botti, Tommaso Barbieri, Davide Luigi Brambilla, Cristiano Meroni
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Publication number: 20220033254Abstract: A MEMS accelerometer includes a supporting structure, at least one deformable group and one second deformable group, which include, respectively, a first deformable cantilever element and a second deformable cantilever element, which each have a respective first end, which is fixed to the supporting structure, and a respective second end. The first and second deformable groups further include, respectively, a first piezoelectric detection structure and a second piezoelectric detection structure. The MEMS accelerometer further includes: a first mobile mass and a second mobile mass, which are fixed, respectively, to the second ends of the first and second deformable cantilever elements and are vertically staggered with respect to the first and second deformable cantilever elements, respectively; and a first elastic structure, which elastically couples the first and second mobile masses.Type: ApplicationFiled: July 26, 2021Publication date: February 3, 2022Applicant: STMicroelectronics S.r.l.Inventors: Gabriele GATTERE, Patrick FEDELI, Carlo VALZASINA
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Publication number: 20220033251Abstract: An electronic device comprises a “waterproof” package including a substrate of an organic material permeable to humidity and/or moisture as well as one or more electronic components arranged on the substrate. The substrate comprises a barrier layer capable of countering penetration of humidity and/or moisture into the package through the organic material substrate.Type: ApplicationFiled: July 30, 2021Publication date: February 3, 2022Applicant: STMICROELECTRONICS S.r.l.Inventors: Alex Gritti, Marco Del Sarto
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Publication number: 20220038094Abstract: An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.Type: ApplicationFiled: July 29, 2021Publication date: February 3, 2022Applicant: STMicroelectronics S.r.l.Inventor: Davide Giuseppe PATTI
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Publication number: 20220038065Abstract: A charge amplifier circuit is provided. The charge amplifier circuit is couplable to a transducer that generates an electrical charge that varies with an external stimulus. The charge amplifier circuit includes an amplification stage having an input node, couplable to the transducer, and an output node. The amplification stage biases the input node at a first direct current (DC) voltage. The charge amplifier circuit includes a feedback circuit, which includes a feedback capacitor, electrically coupled between the input and output nodes of the amplification stage. The feedback circuit includes a resistor electrically coupled to the input node, and a level-shifter circuit, electrically coupled between the resistor and the output node. The level-shifter circuit biases the output node at a second DC voltage and as a function of a difference between the second DC voltage and a reference voltage.Type: ApplicationFiled: October 14, 2021Publication date: February 3, 2022Applicant: STMicroelectronics S.r.l.Inventor: Alberto Danioni
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Patent number: 11237077Abstract: A stress sensor includes: a substrate, having a face and a recess, open to the face; and a sensor chip of semiconductor material, housed in the recess and bonded to the substrate, the sensor chip being provided with a plurality of sensing components of piezoresistive material. The substrate has a thickness which is less by at least one order of magnitude with respect to a main dimension of the face. Further, the sensor chip has a thickness which is less by at least one order of magnitude with respect to the thickness of the substrate, and a Young's module of the substrate and a Young's module of the sensor chip are of the same order of magnitude.Type: GrantFiled: March 14, 2019Date of Patent: February 1, 2022Assignee: STMICROELECTRONICS S.r.l.Inventor: Santo Alessandro Smerzi
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Patent number: 11239796Abstract: An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.Type: GrantFiled: February 20, 2021Date of Patent: February 1, 2022Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (GRENOBLE 2) SASInventors: Daniele Mangano, Benoit Marchand, Santo Leotta, Hamilton Emmanuel Querino De Carvalho
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Patent number: 11239132Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.Type: GrantFiled: June 5, 2020Date of Patent: February 1, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Francesco Salamone, Cristiano Gianluca Stella
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Publication number: 20220028978Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.Type: ApplicationFiled: July 13, 2021Publication date: January 27, 2022Applicant: STMICROELECTRONICS S.R.L.Inventors: Simone RASCUNÁ, Mario Giuseppe SAGGIO
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Publication number: 20220028769Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Applicant: STMicroelectronics S.r.l.Inventor: Federico Giovanni ZIGLIOLI