Patents Assigned to STMicroelectronics SA.A.
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Patent number: 11496049Abstract: A continuous time digital signal processing (CT DSP) token includes a first signal indicating a change has occurred and a second signal indicating a direction of the change. An amplitude generation circuit operates to generate an amplitude value x in response to the token. A power estimation circuit processes the amplitude value x to generate a digital power signal in accordance with the formula: x2±2x+1.Type: GrantFiled: February 13, 2020Date of Patent: November 8, 2022Assignees: Universite de Lille, Centre National De La Recherche Scientifique, ISEN Yncrea Hauts-de-France, STMicroelectronics SAInventors: Angel de Dios Gonzalez Santos, Andreas Kaiser, Antoine Frappe, Philippe Cathelin, Benoit Larras
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Patent number: 11476892Abstract: In an embodiment, a circuit includes first, second, and third 90° hybrid couplers coupled between first and second antenna terminals, a pair of low-noise amplifiers (LNAs), and a pair of power amplifiers (PAs). The pair of LNAs is configured to receive first signals from the first and second antenna terminals and has an output configured to be coupled to a receive path. The second coupler is configured in power combiner mode for receiving the first signals. The pair of PAs is configured to transmit second signals via the first and second antenna terminals and has an input configured to be coupled to a transmit path. The third coupler is configured in power divider mode for transmitting the second signals.Type: GrantFiled: October 20, 2021Date of Patent: October 18, 2022Assignee: STMICROELECTRONICS SAInventors: Jeremie Forest, Vincent Knopik
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Patent number: 11450689Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.Type: GrantFiled: July 13, 2020Date of Patent: September 20, 2022Assignee: STMicroelectronics SAInventors: Thomas Bedecarrats, Philippe Galy
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Patent number: 11451378Abstract: An embodiment encryption method, implemented by an electronic circuit including a first non-volatile memory, comprises the creation of one or more first pairs of asymmetrical keys, the first pair or each of the first pairs comprising first private and public keys, and, for the or at least one of the first pairs, storing the first public key in the first memory, receiving a second public key during a communication session, and forming a first symmetrical key from the first private key and the second public key, the first public key staying stored in the first memory after the communication session.Type: GrantFiled: September 17, 2020Date of Patent: September 20, 2022Assignee: STMICROELECTRONICS SAInventors: Benjamin Baratte, Laurent Halajko
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Patent number: 11444591Abstract: A method for controlling a signal envelope shape of modulation pulses in a driver of a wireless transmitter includes supplying a first voltage to the driver during a non-modulated state, supplying a second voltage configurable by a configurable modulation index value to the driver during a modulated state, switching between the non-modulated state and the modulated state comprising setting the modulation index value to configure the second voltage level at the same level as the first voltage and then switching between supplying the first voltage to the driver and supplying the second voltage to the driver, and filtering to a limited bandwidth the variations of the second voltage resulting from configuring the modulation index value.Type: GrantFiled: June 29, 2020Date of Patent: September 13, 2022Assignees: STMICROELECTRONICS RAZVOJ POLPREVODNIKOV D.O.O., STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS SAInventors: Kosta Kovacic, Christophe Grundrich, Bruno Leduc, Anton Stern
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Patent number: 11444077Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.Type: GrantFiled: November 26, 2019Date of Patent: September 13, 2022Assignee: STMicroelectronics SAInventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
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Publication number: 20220239539Abstract: An OFDM (orthogonal frequency division multiplexing) transmitter includes an inverse fast Fourier transform circuit, which, in operation, generates, based on digital input data, a complex time-varying digital signal having real and imaginary components; and a multiplexer adapted to generate a time-multiplexed digital signal by time-multiplexing one or more of the real components with one or more of the imaginary components.Type: ApplicationFiled: April 15, 2022Publication date: July 28, 2022Applicant: STMICROELECTRONICS SAInventor: Fatima BARRAMI
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Patent number: 11394101Abstract: A hybrid coupler operating in a power divider mode includes two inputs, two outputs, a capacitive module coupled between the inputs and the outputs or on each input and each output. The capacitive module has an adjustable capacitive value making it possible to adjust the central frequency. A calibration method includes: delivering a first reference signal having a first reference frequency on the first input of the hybrid coupler, measuring the peak value of a first signal delivered to the first output of the coupler and measuring the peak value of a second signal delivered to the second output of the coupler. The two peak values are compared and an adjustment of the capacitive value of the capacitive module is made until an equality of the peak values is obtained to within a tolerance.Type: GrantFiled: November 21, 2017Date of Patent: July 19, 2022Assignee: STMicroelectronics SAInventors: Vincent Knopik, Jeremie Forest, Eric Kerherve
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Patent number: 11391624Abstract: A light sensor includes a first pixel and a second pixel. Each pixel has a photoconversion area. A band-stop Fano resonance filter is arranged over the first pixel. The second pixel includes no Fano resonance filter. Signals output from the first and second pixels are processed to determine information representative of the quantity of light received by the light sensor during an illumination phase in a rejection band of the band-stop Fano resonance filter.Type: GrantFiled: December 9, 2020Date of Patent: July 19, 2022Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Olivier Le Neel, Stephane Monfray
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Patent number: 11385288Abstract: A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The comparing and the shifting and storing are repeated until all the stored test data has been compared. The at least three devices may have a same functionality and a same structure.Type: GrantFiled: September 24, 2020Date of Patent: July 12, 2022Assignee: STMICROELECTRONICS SAInventors: Ricardo Gomez Gomez, Sylvain Clerc
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Patent number: 11387354Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.Type: GrantFiled: May 8, 2020Date of Patent: July 12, 2022Assignee: STMicroelectronics SAInventors: Philippe Galy, Louise De Conti
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Patent number: 11380766Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.Type: GrantFiled: June 7, 2019Date of Patent: July 5, 2022Assignee: STMicroelectronics SAInventors: Sotirios Athanasiou, Philippe Galy
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Patent number: 11374597Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: GrantFiled: May 24, 2021Date of Patent: June 28, 2022Assignee: STMICROELECTRONICS SAInventors: Pierre Dautriche, Sylvain Engels
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Publication number: 20220199133Abstract: A memory includes memory cells arranged in rows and in columns, with at least one bit line for each column being coupled to the memory cells of the column. A read/write circuit is coupled to the bit lines and is configured to receive, for each column, a binary datum to be stored in one of the memory cells of the column. The read/write circuit includes, for each column, a latch configured to store a bit of a key, and an encryption circuit configured to encrypt the received binary datum with the bit of the key to provide encrypted binary datum. The read/write circuit controls the bit line to thereby store the encrypted binary datum.Type: ApplicationFiled: December 20, 2021Publication date: June 23, 2022Applicant: STMicroelectronics SAInventor: Faress TISSAFI DRISSI
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Publication number: 20220199648Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.Type: ApplicationFiled: December 7, 2021Publication date: June 23, 2022Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Olivier WEBER, Christophe LECOCQ
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Publication number: 20220190140Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.Type: ApplicationFiled: March 3, 2022Publication date: June 16, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Alexis GAUTHIER, Pascal CHEVALIER
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Patent number: 11355503Abstract: A device includes at least three memory cells. For each cell, there is a first doped semiconductor area and a switch coupling the cell to the first area. First doped semiconductor zones connect the first areas together. A memory can include a number of the devices. For example, the cells can be arranged in a matrix, each device defining a row of the matrix.Type: GrantFiled: December 10, 2019Date of Patent: June 7, 2022Assignee: STMICROELECTRONICS SAInventors: Stephane Denorme, Philippe Candelier
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Patent number: 11355851Abstract: A first independent unit includes a support substrate with an integrated network of electrical connections. An electronic integrated circuit chip is mounted above a front face of the support substrate. A second independent unit includes a dielectric support. The second independent unit is stacked above the first independent unit on a side of the front face of the first independent unit. An electromagnetic antenna includes an exciter element and a resonator element. The exciter element provided at the support substrate. The resonator element is provided at the dielectric support.Type: GrantFiled: June 1, 2020Date of Patent: June 7, 2022Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble 2) SASInventors: Frederic Gianesello, Didier Campos
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Patent number: 11353508Abstract: A method tests a plurality of devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices. The test data in the test chains of the devices is shifted forward by one position. The shifting includes writing test data in the last position of a test chain to a first position in the test chain. The comparing and the shifting are repeated until the test data in the last position of each test chain when the testing is started is shifted back into the last position of the respective test chain. The plurality of devices may have a same structure and a same functionality.Type: GrantFiled: September 24, 2020Date of Patent: June 7, 2022Assignee: STMICROELECTRONICS SAInventor: Ricardo Gomez Gomez
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Publication number: 20220160314Abstract: An X-ray detector includes a first circuit with an NPN-type bipolar transistor and a second circuit configured to compare a voltage at a terminal of the NPN-type bipolar transistor with a reference value substantially equal to a value of the terminal voltage which would occur when the first circuit has been exposed to a threshold quantity of X-rays.Type: ApplicationFiled: November 18, 2021Publication date: May 26, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Gilles GASIOT, Severin TROCHUT, Olivier LE NEEL, Victor MALHERBE
