Patents Assigned to STMicroelectronics SA.A.
  • Low leakage MOSFET supply clamp for electrostatic discharge (ESD) protection
    Patent number: 11063429
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 13, 2021
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan Sithanandam, Divya Agarwal, Ghislain Troussier, Jean Jimenez, Malathi Kar
  • COMPACT PROTECTION DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGE
    Publication number: 20210193648
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Application
    Filed: March 3, 2021
    Publication date: June 24, 2021
    Applicant: STMicroelectronics SA
    Inventor: Johan BOURGEAT
  • LIGHT SENSOR
    Publication number: 20210172791
    Abstract: A light sensor includes a first pixel and a second pixel. Each pixel has a photoconversion area. A band-stop Fano resonance filter is arranged over the first pixel. The second pixel includes no Fano resonance filter. Signals output from the first and second pixels are processed to determine information representative of the quantity of light received by the light sensor during an illumination phase in a rejection band of the band-stop Fano resonance filter.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 10, 2021
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier LE NEEL, Stephane MONFRAY
  • ELECTRONIC ENVELOPE DETECTION CIRCUIT AND CORRESPONDING DEMODULATOR
    Publication number: 20210167729
    Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Applicant: STMicroelectronics SA
    Inventor: Lionel VOGT
  • Sampling circuit
    Patent number: 11005490
    Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 11, 2021
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS SA
    Inventors: Stéphane Le Tual, David Duperray, Jean-Pierre Blanc
  • Integrated coupling device, in particular of the 90° hybrid type
    Patent number: 10985437
    Abstract: A 90° hybrid inductive-capacitive coupling stage includes two first stage terminals capable of forming two stage inputs or two stage outputs and two second stage terminals capable of respectively forming two stage outputs or two stage inputs. The coupling stage is advantageously modular having a first stage axis of symmetry and a second stage axis of symmetry orthogonal to each other with neighboring inductive metal tracks being overlaid in at least one crossing region to form both an inductive circuit and a capacitive circuit. The metal tracks are coupled to the first stage terminals and to the second stage terminals such that the two first stage terminals are situated on one side of the first stage axis of symmetry and the two second stage terminals are situated on the other side of the first stage axis of symmetry.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: April 20, 2021
    Assignee: STMicroelectronics SA
    Inventors: Vincent Knopik, Boris Moret, Eric Kerherve
  • Method for managing access to a shared bus and corresponding electronic device
    Patent number: 10983937
    Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: April 20, 2021
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS SA
    Inventors: Olivier Ferrand, Daniel Olson, Anis Ben Said, Emmanuel Ardichvili
  • Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure
    Patent number: 10978340
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 13, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Didier Dutartre, Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster
  • Method of manufacturing a waveguide
    Patent number: 10976494
    Abstract: A method of manufacturing an optical device is disclosed. The method includes scanning along a curved path at a first surface of a glass plate with a laser beam directed orthogonally to the first surface to form a trench according to a pattern of a waveguide. The curved path is coincident with a longitudinal axis of the waveguide. The method further includes filling the trench with a material having an index different from that of glass to form the waveguide and, after filling the trench, depositing a cladding layer.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 13, 2021
    Assignee: STMICROELECTRONICS SA
    Inventors: Cédric Durand, Frédéric Gianesello, Folly Eli Ayi-Yovo
  • Inverting circuit
    Patent number: 10978487
    Abstract: An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: April 13, 2021
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Hassan El Dirani, Pascal Fonteneau
  • Remotely powered contactless card
    Patent number: 10978910
    Abstract: A contactless card is powered by an antenna connected to the input of a rectifier. An output of the rectifier is coupled to a processing unit that consumes a first current output from the rectifier. A current regulation circuit is connected to the output of the rectifier. The current regulation circuit operates to absorb a second current from the output of the rectifier such that a sum of the first and second currents is a constant current.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 13, 2021
    Assignee: STMicroelectronics SA
    Inventor: Julien Goulier
  • Compact protection device for protecting an integrated circuit against electrostatic discharge
    Patent number: 10971489
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Integrated optical switch
    Patent number: 10972097
    Abstract: In accordance with an embodiment of the present invention, an optical switch includes a photoconductor body including a first edge and an opposite second edge, a first end and an opposite second end. The first edge is configured to receive an electrical input signal and the second edge is configured to deliver an electrical output signal. The photoconductor body is configured to have an electrically ON state that is activated by an optical signal and an electrically OFF state that is activated by an absence of the optical signal. A direction from the first end to the second end defines a longitudinal direction. The direction from the first edge to the second edge defines a first direction that is orthogonal to the longitudinal direction. A first dimension between the first edge and the second edge along the first direction decreases from the first end to the second end.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS SA
    Inventors: Hanae Zegmout, Denis Pache, Stephane Le Tual, Jean-François Roux, Jean-Louis Coutaz
  • LIGHT SENSOR
    Publication number: 20210088378
    Abstract: A light sensor includes a semiconductor substrate supporting a number of pixels. Each pixel includes a photoconversion zone extending in the substrate between a front face and a back face of the substrate. An optical diffraction grating is arranged over the back face of the substrate at a position facing the photoconversion zone of the pixel. For at least two different pixels of the light sensor, the optical diffraction gratings have different pitches. Additionally, the optical grating of each pixel is surrounded by an opaque wall configured to absorb at operating wavelengths of the sensor.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Stephane MONFRAY, Olivier LE NEEL, Frederic BOEUF
  • Electronic envelope detection circuit and corresponding demodulator
    Patent number: 10951168
    Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: March 16, 2021
    Assignee: STMicroelectronics SA
    Inventor: Lionel Vogt
  • Integrated silicon controlled rectifier (SCR) and a low leakage SCR supply clamp for electrostatic discharge (ESP) protection
    Patent number: 10944257
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 9, 2021
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan Sithanandam, Divya Agarwal, Jean Jimenez, Malathi Kar
  • Electronic device forming a digital-to-analog converter and a mixer
    Patent number: 10917106
    Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 9, 2021
    Assignees: STMicroelectronics SA, STMicroelectronics (Alps) SAS
    Inventors: Stephane Le Tual, Jean-Pierre Blanc, David Duperray
  • PROTECTING AN INTEGRATED CIRCUIT FROM THE DRILLING OF A SOURCE AND/OR DRAIN CONTACT
    Publication number: 20210020663
    Abstract: An integrated circuit includes a MOS transistor that is located in and on a semiconductor film of a silicon-on-insulator (SOI) substrate. The SOI substrate has, below a buried insulator layer, a first back gate region and two first auxiliary regions that are located, respectively, below source and drain contact regions of the MOS transistor. The conductivity type of the two first auxiliary regions is the opposite the conductivity type of the first back gate region. The conductivity type of the two first auxiliary regions is identical to the conductivity type of the source and drain contact regions of the MOS transistor.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 21, 2021
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Thomas BEDECARRATS
  • INTEGRATED CIRCUIT WITH DOUBLE ISOLATION OF DEEP AND SHALLOW TRENCH-ISOLATION TYPE
    Publication number: 20210020660
    Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.
    Type: Application
    Filed: July 13, 2020
    Publication date: January 21, 2021
    Applicant: STMicroelectronics SA
    Inventors: Thomas BEDECARRATS, Philippe GALY
  • LOW LEAKAGE MOSFET SUPPLY CLAMP FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
    Publication number: 20200412124
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 31, 2020
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Ghislain TROUSSIER, Jean JIMENEZ, Malathi KAR