Patents Assigned to STMicroelectronics SA.A.
  • Methods of fabricating integrated circuit devices with components on both sides of a semiconductor layer
    Patent number: 10877211
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • Switched-mode power converter
    Patent number: 10862395
    Abstract: A switched-mode power converter device includes an inductive element coupling a first node receiving an input voltage to a second node. A first transistor couples the second node to a third node generating an output voltage. A control circuit includes a first switch coupling the third node to a control terminal of the first transistor.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: December 8, 2020
    Assignee: STMicroelectronics SA
    Inventors: Francois Agut, Severin Trochut
  • ELECTRONIC DEVICE COMPRISING AN INTEGRATED ELECTROMAGNETIC ANTENNA
    Publication number: 20200381833
    Abstract: A first independent unit includes a support substrate with an integrated network of electrical connections. An electronic integrated circuit chip is mounted above a front face of the support substrate. A second independent unit includes a dielectric support. The second independent unit is stacked above the first independent unit on a side of the front face of the first independent unit. An electromagnetic antenna includes an exciter element and a resonator element. The exciter element provided at the support substrate. The resonator element is provided at the dielectric support.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 3, 2020
    Applicants: STMicroelectronics SA, STMicroelectronics (Grenoble 2) SAS
    Inventors: Frederic GIANESELLO, Didier CAMPOS
  • POLARIZATION-SPLITTING GRANTING COUPLER (PSGC) INTEGRATED OPTOELECTRONIC OR OPTICAL DEVICE
    Publication number: 20200379178
    Abstract: An integrated optoelectronic or optical device is formed by a polarization-splitting grating coupler including two optical waveguides, a common optical coupler and flared optical transitions between the optical coupler and the optical waveguides. The optical coupler is configured for supporting input/output of optical waves. A first region of the optical coupler lies at a distance from the flared optical transitions. The first region includes a first recessed pattern. Second regions of the optical coupler lie between the first region and the flared optical transitions, respectively, in an adjoining relationship. The second regions include a second recessed pattern different from the first recessed pattern.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 3, 2020
    Applicant: STMicroelectronics SA
    Inventors: Frederic GIANESELLO, Ophelie FOISSEY, Cedric DURAND
  • Device for generating a random signal
    Patent number: 10853038
    Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 1, 2020
    Assignee: STMICROELECTRONICS SA
    Inventors: Philippe Galy, Thomas Bedecarrats
  • DATA TRANSMISSION, IN PARTICULAR ON A SERIAL LINK HAVING A GREAT LENGTH
    Publication number: 20200373965
    Abstract: Binary data is processed through a differential pre-encoder, which includes a simple modulo-2 addition. This step is used to cancel the propagation error that can be introduced by duo-binary modulation and to simplify demodulation. Next the duo-binary encoder introduces controlled Inter Symbol Interference between a previously sent bit and a present bit to compress the spectral density closer to the DC. Next a 60-GHz carrier is modulated and transmitted over differential transmission lines.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 26, 2020
    Applicant: STMicroelectronics SA
    Inventors: Mohammed TMIMI, Philippe GALY
  • Synchronization between a reader and an object in contactless communication with the reader by active load modulation
    Patent number: 10841887
    Abstract: Data frames, including bursts of an active load modulation (ALM) carrier signal generated from a modulation of an underlying carrier, are transmitted from an object to a reader. Synchronizing a reader carrier signal and the ALM carrier signal includes: prior to transmission of each data frame and between some of the bursts of the ALM carrier signal of each data frame, performing a closed-loop control of an output signal of a main oscillator onto a phase and a frequency of the reader carrier signal; estimating a ratio between a frequency of the output signal of the main oscillator and a frequency of a reference signal produced by a reference oscillator; and during each burst of the ALM carrier signal of each data frame, performing a closed-loop control in frequency only of the output signal of the main oscillator onto the reference frequency of the reference signal corrected by the ratio.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: November 17, 2020
    Assignee: STMICROELECTRONICS SA
    Inventor: Marc Houdebine
  • Method for synchronizing an active load modulation clock within a transponder, and corresponding transponder
    Patent number: 10841074
    Abstract: A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 17, 2020
    Assignees: STMicroelectronics SA, STMicroelectronics Razvoj Polprevodnikov d.o.o.
    Inventors: Maksimiljan Stiglic, Nejc Suhadolnik, Marc Houdebine
  • BIMOS TRANSISTOR
    Publication number: 20200357902
    Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Louise DE CONTI
  • ELECTRONIC CIRCUIT
    Publication number: 20200357788
    Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: STMicroelectronics SA
    Inventors: Louise DE CONTI, Philippe GALY
  • METHOD AND DEVICE FOR CALIBRATING A HYBRID COUPLER
    Publication number: 20200350653
    Abstract: A hybrid coupler operating in a power divider mode includes two inputs, two outputs, a capacitive module coupled between the inputs and the outputs or on each input and each output. The capacitive module has an adjustable capacitive value making it possible to adjust the central frequency. A calibration method includes: delivering a first reference signal having a first reference frequency on the first input of the hybrid coupler, measuring the peak value of a first signal delivered to the first output of the coupler and measuring the peak value of a second signal delivered to the second output of the coupler. The two peak values are compared and an adjustment of the capacitive value of the capacitive module is made until an equality of the peak values is obtained to within a tolerance.
    Type: Application
    Filed: November 21, 2017
    Publication date: November 5, 2020
    Applicant: STMicroelectronics SA
    Inventors: Vincent KNOPIK, Jeremie FOREST, Eric KERHERVE
  • Method and device for measuring the frequency of a signal
    Patent number: 10823771
    Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 3, 2020
    Assignee: STMICROELECTRONICS SA
    Inventors: Marc Houdebine, Sebastien Dedieu
  • Memory array comprising memory cells of Z2-FET type
    Patent number: 10804275
    Abstract: A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics SA
    Inventors: Hassan El Dirani, Thomas Bedecarrats, Philippe Galy
  • Flip-flop with a metal programmable initialization logic state
    Patent number: 10804885
    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • Device and method for processing a histogram of arrival times in an optical sensor
    Patent number: 10796191
    Abstract: An example device has optical emitters for emitting incident radiation within a field of view and optical detectors for receiving reflected radiation. Based on the incident radiation and the reflected radiation, a histogram indicative of a number of photon events that are detected by the optical detectors over time bins is generated. The time bins is indicative of time differences between emission of the incident radiation and reception of the reflected radiation. The device further includes; a processor programmed to iteratively process the histogram by executing an expectation-maximization algorithm to detect a presence of objects located in the field of view of the device.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 6, 2020
    Assignees: STMicroelectronics SA, STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Francois De Salivet de Fouchecour, Stuart McLeod, Donald Baxter, Olivier Pothier, Thierry Lebihen
  • Electronic device providing a temperature sensor or a current source delivering a temperature independent current
    Patent number: 10795396
    Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics SA
    Inventors: Renan Lethiecq, Philippe Galy
  • Method for manufacturing an optical device
    Patent number: 10782468
    Abstract: The present invention relates to a method for manufacturing an optical device comprising forming a first trench in a glass plate and a second trench perpendicular to the first trench, wherein the first trench has an end opening into the second trench. The trenches are treated with hydrofluoric acid. The first trench is filled with a material to form a waveguide, and a mirror is formed on the wall of the second trench opposite the waveguide. An encapsulation layer is deposited over the glass plate, waveguide and second trench.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: September 22, 2020
    Assignee: STMICROELECTRONICS SA
    Inventors: Folly Eli Ayi-Yovo, Cédric Durand, Frédéric Gianesello
  • Measurement of the duration of a pulse
    Patent number: 10771048
    Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 8, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Capucine Lecat-Mathieu De Boissac, Fady Abouzeid, Gilles Gasiot, Philippe Roche, Victor Malherbe
  • MEASUREMENT OF THE DURATION OF A PULSE
    Publication number: 20200252059
    Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.
    Type: Application
    Filed: January 20, 2020
    Publication date: August 6, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Capucine LECAT-MATHIEU DE BOISSAC, Fady ABOUZEID, Gilles GASIOT, Philippe ROCHE, Victor MALHERBE
  • ELECTRONIC ENVELOPE DETECTION CIRCUIT AND CORRESPONDING DEMODULATOR
    Publication number: 20200228061
    Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 16, 2020
    Applicant: STMicroelectronics SA
    Inventor: Lionel VOGT