Abstract: An embodiment near-field communication device using active load modulation, in card emulation mode and intended to communicate with a reader, comprises a digital phase-locked loop configured to generate a carrier signal, having an oscillator configured to generate the carrier signal in a manner controlled by an analog control signal, a feedback circuit configured to generate a digital control signal, a digital-to-analog converter configured to convert the digital control signal into the analog control signal, and an integrator assembly configured to integrate the analog control signal.
Abstract: A low-dropout regulator includes a power stage having an output terminal coupled to a load circuit operable in different operating modes in which it receives different output currents. An error amplifier has a first input coupled to a reference voltage and an output coupled to an input terminal of the power stage. A compensation circuit includes a first stage with an RC filter coupled to the input terminal of the power stage, and generating an initial compensation voltage. A second stage includes a first transistor coupled between a supply voltage and a second node, and controlled by a complementary control signal, a high-side capacitor coupled between the second node and ground, and a third transistor coupled between the initial compensation voltage and the second node, and controlled by a control signal representative of the current operating mode of the load circuit.
Abstract: An image sensor includes a plurality of pixels, where each of the plurality of pixels includes a photodiode. The image sensor is configured to capture images of a scene exposed with a flickering light source by for each of the plurality of pixels, acquiring a value representative of a light level at a corresponding pixel by gradually varying a value of sensitivity of the corresponding pixel.
Type:
Grant
Filed:
November 22, 2019
Date of Patent:
November 23, 2021
Assignees:
STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS SA
Abstract: A device includes a number of irreversibly programmable memory points. Each irreversibly programmable memory point includes a first semiconductor zone and a gate located on the first zone. A conductive area defines the gates of the memory points. First and second semiconductor areas are respectively located on either side of a vertical alignment with the conductive area. The first zones are alternately in contact with the first and second areas.
Abstract: An embodiment electronic device comprises at least two antennas for transmitting signals, and at least one transmission path, the transmission path including a first coupling stage including a power divider, variable-gain power amplifiers, and a second coupling stage including a power combiner. Each coupling stage includes two inputs and two outputs, the two inputs of the first coupling stage being configured to receive a power input signal. Each output of the first coupling stage is connected to a different input of the second coupling stage via the variable-gain power amplifiers, and each output of the second coupling stage is connected to a different antenna. A controller is configured to control the gains of the variable-gain power amplifiers according to the characteristics of the power input signal, the signals transmitted by the antennas, and the coupling stages.
Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.
Type:
Grant
Filed:
December 7, 2018
Date of Patent:
October 19, 2021
Assignees:
STMICROELECTRONICS SA, INSTITUT POLYTECHNIQUE DE GRENOBLE
Inventors:
Sophie Germain, Sylvain Engels, Laurent Fesquet
Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.
Type:
Grant
Filed:
October 2, 2019
Date of Patent:
October 12, 2021
Assignees:
STMicroelectronics (Grolles 2) SAS, STMicroelectronics SA
Abstract: Requests are received by a routing circuit. A plurality of first round-robin arbitration circuits are coupled to the routing circuit. There are as many first round-robin arbitration circuits as there are possible priority levels for the requests. The routing circuit operates to transmit each received request to a number of first round-robin arbitration circuits determined according to the priority level of the request. A second round-robin arbitration circuit has inputs respectively connected to the outputs of the first round-robin arbitration circuits.
Type:
Grant
Filed:
January 10, 2020
Date of Patent:
October 5, 2021
Assignees:
STMicroelectronics SA, STMicroelectronics (Grenoble 2) SAS
Abstract: The method of determination of a depth map of a scene comprises generation of a distance map of the scene obtained by time of flight measurements, acquisition of two images of the scene from two different viewpoints, and stereoscopic processing of the two images taking into account the distance map. The generation of the distance map includes generation of distance histograms acquisition zone by acquisition zone of the scene, and the stereoscopic processing includes, for each region of the depth map corresponding to an acquisition zone, elementary processing taking into account the corresponding histogram.
Type:
Grant
Filed:
August 22, 2019
Date of Patent:
October 5, 2021
Assignee:
STMICROELECTRONICS SA
Inventors:
Manu Alibay, Olivier Pothier, Victor Macela, Alain Bellon, Arnaud Bourge
Abstract: A variable-gain amplifier includes two amplification and attenuation branches, and first and a second resistive elements that are coupled between the two branches. Each branch includes a voltage follower stage and a configurable amplification stage. The voltage follower stages are intended to receive a differential signal and are configured to deliver, via the first resistive element, an intermediate differential current signal. The amplification stages are intended to receive the intermediate differential current signal and a digital control word, and are configured to deliver, via the second resistive element, an output differential voltage signal depending on the value of the digital control word.
Abstract: A connector includes a first antenna configured to transmit first signals in a first direction and with a first polarization, a second antenna coupled to the first antenna and configured to transmit second signals in a second direction that is parallel to the first direction and with a second polarization that is orthogonal to the first polarization, and a third antenna coupled to the first and second antennas and configured to transmit third signals in a third direction that is parallel to the first direction and with the first polarization, wherein the second antenna is positioned between the first and third antennas.
Abstract: A system has an array of pixels including a plurality of active pixels and a plurality of dark reference pixels and processing circuitry coupled to the array of pixels. The processing circuitry sequentially computes, for each of a plurality of pairs of sets of dark reference pixels of the plurality of dark reference pixels, absolute differences in dark signal levels of the pair of sets of dark reference pixels. The absolute differences in dark signal levels are accumulated and a noise level of the dark reference pixels of the array of pixels is estimated based on the accumulated absolute differences. The system may be employed in, for example, a back-up camera of an automobile or a mobile phone.
Type:
Grant
Filed:
December 11, 2019
Date of Patent:
September 21, 2021
Assignee:
STMICROELECTRONICS SA
Inventors:
Arnaud Bourge, Antoine Drouot, Gwladys Hermant
Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
Abstract: A ring oscillator includes a chain of logic components. A storage element is associated with each logic component and configured to store a state of an output of the logic component to which the storage element is associated. A first circuit counts state transitions of an output of a given logic component of the chain. A second circuit synchronizes each storage with a clock signal. A third circuit determines a number of logic components crossed by a state transition between two edges of the clock signal. This determination is made based on the counted number of state transitions and on the stored states of the outputs.
Abstract: A low-dropout voltage regulation device includes a power stage having an output terminal coupled to a load circuit, the load circuit being operable in a plurality of operating modes. The load circuit is configured to receive a different respective output current when in each of the plurality of operating modes. An error amplifier has an output coupled to an input terminal of the power stage. A compensation circuit is coupled to the input terminal of the power stage and is operable in a plurality of selectable configurations that are respectively tailored to the plurality of operating modes. The plurality of selectable configurations are selectable in response to a control signal representative of a current operating mode of the load circuit.
Abstract: The present disclosure relates to a tone mapping method for a succession of images implemented by an image processing device. The method including a) the division of the images of the succession of images in a plurality of sub-blocks of first pixels; b) for a first image (INPUT_IMAGEf) of the succession of images, the creation of a first mini-image (MPICf) comprising pixels of the first mini-image, each pixel of the first mini-image representing a corresponding sub-block of the first image, the intensity of each pixel of the first mini-image being representative of the intensity of the first pixels of the corresponding sub-block; c) the storage of the first mini-image (MPICf) in a memory; and d) for a second image (INPUT_IMAGEf+1) of the succession of images, the modification of the second image according to the first mini-image (MPICf) in order to generate an output image.
Type:
Application
Filed:
February 4, 2021
Publication date:
August 26, 2021
Applicants:
STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMICROELECTRONICS SA
Inventors:
Héloïse Eliane Geneviève GRESSET, Brian Douglas STEWART
Abstract: A continuous time digital signal processing (CT DSP) token includes a first signal indicating a change has occurred and a second signal indicating a direction of the change. An amplitude generation circuit operates to generate an amplitude value x in response to the token. A power estimation circuit processes the amplitude value x to generate a digital power signal in accordance with the formula: x2±2x+1.
Type:
Application
Filed:
February 13, 2020
Publication date:
August 19, 2021
Applicants:
Universite de Lille, Centre National De La Recherche Scientifique, ISEN Yncrea Hauts-de-France, STMicroelectronics SA
Inventors:
Angel de Dios GONZALEZ SANTOS, Andreas KAISER, Antoine FRAPPE, Philippe CATHELIN, Benoit LARRAS
Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.